CALL FOR PAPERS
ISQED 2003
4th International Symposium on
QUALITY ELECTRONIC DESIGN

     March 17-20, 2003
     DoubleTree Hotel, San Jose, CA, USA
     http://www.isqed.org


ISQED 2003 is a premier Design and Design Automation conference,
held in cooperation with IEEE Computer Society; Test Technology
Technical Council (TTTC), Design Automation & VLSI Technical
Committees, IEEE Electron Device Society, ACM/sigDA, and Fabless
Semiconductor Association (FSA).  Conference proceedings are
published by IEEE Computer Society.  The conference spans for four
days, Monday through Thursday, in four parallel tracks, hosting
over 100 technical presentations, eight keynote speakers, two
panel discussions, poster sessions, student forum sessions, and
other fringe meetings.


PAPERS ARE REQUESTED IN THE FOLLOWING AREAS

DESIGN FOR TESTABILITY (DFT)
 DFT and BIST, DFT for analog/mixed-signal ICs and systems-on-chip,
 DFT/BIST for memories.  Test synthesis and synthesis for
 testability.  DFT economics, DFT case studies.  DFT and ATE.
 Fault diagnosis, IDDQ test, novel test methods, effectiveness of
 test methods, fault models and ATPG, and DPPM prediction.  SoC/IP
 testing strategies.

DESIGN FOR MANUFACTURABILITY (DFM)
 Analysis, modeling, and abstraction of manufacturing process
 parameters and effects for highly predictable silicon performance.
 Design and synthesis of high complexity ICs:  signal integrity,
 transmission line effects, OPC, Phase Shifting, and sub-wavelength
 lithography, manufacturing yield and technology capability.
 Design for diagnosability, defect detection and tolerance;
 self-diagnosis, calibration and repair.  Design and
 manufacturabilty issues for analog, mixed signal, MEMS,
 opto-electronic and biochemical-electronic ICs; design and
 manufacturing issues for nanotechnology based ICs.  Redundancy and
 other yield improving techniques.

DEVICE, INTERCONNECT AND CIRCUIT LEVEL MODELING AND ANALYSIS (DEV)
 Device, substrate, interconnect, circuit , and IP block modeling
 and simulation techniques; quality metrics, model order reduction;
 SiGe HBTs and CMOS device modeling in the context of RF and
 high-speed circuits.  Modeling and simulation of novel device and
 interconnect concepts such as single electron transistors (SET),
 hybrid SET-FET architectures, 3-D ICs, optical interconnects, etc.
 Signal integrity analysis:  coupling, inductive and charge sharing
 noise; noise avoidance techniques.  Power grid design, analysis
 and optimization; timing analysis and optimization; thermal
 analysis and design techniques for thermal management.  Modeling
 statistical process variations to improve design margin and
 robustness, use of statistical circuit simulators.

EDA TOOLS, INTEROPERABILITY AND IMPLICATIONS (EDA)
 EDA tools addressing design quality.  EDA tools interoperability
 issues and implications.  Management of design process, and design
 database.  Effect of emerging processes & devices on design flows,
 tools, and tool interoperability.  Emerging EDA standards.  EDA
 design methodologies and tools that address issues which impact
 the quality of the realization of designs into physical integrated
 circuits.

LOW POWER DESIGN AND TEST (LPD)
 Power-conscious design methodologies and tools; low power devices,
 circuits and systems; power-aware computing and communication;
 system-level power optimization and management.  Design for:
 test, manufacturing, debug, repair, and yield.  System-on-Chip
 test; memory, microprocessor, mixed-signal and analog test.
 Design techniques for leakage current management.

METHODOLOGIES AND METRICS FOR DESIGN QUALITY (MDQ)
 Design quality definitions and standards; design quality metrics
 to track and assess the quality of electronic circuit design, as
 well as the quality of the design process itself; design quality
 assurance techniques.  Global, social, and economic implications
 of design quality.  Design metrics, methodologies and flows for
 custom, semi-custom, ASIC, FPGA, RF, memory, networking circuit,
 etc. with emphasis on quality.  Design metrics and quality
 standards for SoC, and SiP.

PACKAGE - DESIGN INTERACTIONS & CO-DESIGN (PDI)
 Packaging electrical and thermal modeling and simulation for
 improved quality of product.  SoC versus system in a package
 (SiP):  design and technology solutions and tradeoffs; MCM and
 other packaging techniques; heat sink technology.  Concurrent
 circuit and package design and effect on quality.

PHYSICAL DESIGN, METHODOLOGIES & TOOLS (PDM)
 Physical synthesis flows for correct-by-construction quality
 silicon, implementation of large SoC designs.  Tool frameworks and
 data models for tightly integrated incremental synthesis,
 placement, routing, timing analysis and verification.  Placement,
 optimization, and routing techniques for noise sensitivity
 reduction and fixing.  Algorithms and flows for harnessing
 crosstalk-delay during physical synthesis.  Tool flows and
 techniques for antenna rule and electromigration rule avoidance
 and fixing.  Spare-cell strategies for ECO, decoupling capacitance
 and antenna rule fixing.  Planning tools for predictable
 high-current, low-voltage power distribution.  Reliable clock tree
 generation and clock distribution methodologies for Giga hertz
 designs.  EDA tools, design techniques, and methodologies, dealing
 with issues such as:  timing closure, R, L, C extraction,
 ground/Vdd bounce, signal noise/cross-talk /substrate noise,
 voltage drop, power rail integrity, electromigration, hot !
 carriers, EOS/ESD, plasma induced damage and other yield limiting
 effects, high frequency effects, thermal effects, power
 estimation, EMI/EMC, proximity correction & phase shift methods,
 verification (layout, circuit, function, etc.), packaging modeling
 and simulations.

DESIGN AND ABSTRACTION METHODS FOR SOCS, IP BLOCKS AND LIBRARIES
(SIL)
Challenges and solutions of the integration, testing, and
 qualifying of multiple IP blocks.  IP authoring tools and
 methodologies.  Methods and tools for design and maintenance of
 technology independent hard and soft IP blocks.  Multiple clock
 domains and frequencies, PLLs and on-chip generated clocks.
 Design, abstraction and integration methods for processors, buses,
 ASIC blocks, embedded software, multiple embedded memories, and
 analog mixed signal components.  Virtual socket interfaces,
 interconnect solutions and core access mechanisms.  Wrapper design
 for embedded core test.  IEEE P1500 and other standards for test
 interoperability of cores.  Wrapper architectures and modes.
 Mapping to design libraries, process libraries, design spaces,
 firmness levels, business spaces and levels of proprietary.  Risk
 management of IP reuse.  Tools and methods for comparison of
 libraries and hard IP blocks.  Third party testing of IP blocks.

EFFECTS OF TECHNOLOGY ON IC DESIGN, PERFORMANCE, RELIABILITY, AND
YIELD (TRD)
Emerging issues in DSM CMOS:  e.g. sub-threshold leakage, gate
 leakage, technology road mapping and technology extrapolation
 techniques.  New technologies such as SOI, Double-Gate(DG)-MOSFET,
 Gate-All-Around (GAA)-MOSFET, Vertical-MOSFET, strained CMOS,
 high-bandwidth metallization, etc.  Challenges of mixed-signal
 design in digital CMOS or BiCMOS technology, including issues of
 substrate coupling, cross-talk and power supply noise.
 Significance of reliability effects such as gate oxide integrity,
 electromigration, ESD, etc., in relation to electronic design.
 Impacts of process technologies on circuit design and capabilities
 (e.g. low-Vt transistors versus increased off-state leakages) and
 the accuracy, use and implementation of SPICE models that
 faithfully reflect process technologies, closer applications of
 TCAD to circuit design.

SUBMISSION OF PAPERS
 Three PDF files are required from authors; i) the full-length
 manuscript ii) the 200 words abstract and iii) a cover letter.
 Authors should submit FULL-LENGTH, original, unpublished papers
 (Minimum 4, maximum 6 pages) along with an abstract of about 200
 words.  To permit a blind review, do not include name(s) or
 affiliation(s) of the author(s) on the manuscript and abstract.
 Include the complete contact author information in a separate file
 (cover letter).  Cover letter must include:

 I Title of the paper
 II Name, affiliation, complete mailing address and phone, fax, and
    email of the first author
 III Name, affiliations, city, state, country of additional authors
 IV Person to whom correspondence should be sent, if other than the
    1st author
 V Identification as invited paper if applicable
 VI Suggested area (as listed in previous page)

 Guidelines for the final paper format is provided on the
 conference web site at http://www.isqed.org.

 Electronic submission via e-mail is the only accepted submission
 mode.  Please email your paper in Adobe PDF format to
 widerkehr@isqed.org.  Please check the as-printed appearance of
 your paper before sending your paper.  Authors agree to present
 the paper if it is accepted and need to obtain their company
 approval for publication.  Please note the following important
 dates:

 Paper Submission Deadline September 15, 2002
 Acceptance Notifications November 1, 2002
 Final Camera-Ready paper December 15, 2002


SUBMISSION OF TUTORIAL PROPOSALS
 Several tutorial sessions will be held on the first day, where
 presentations by many industry experts would offer valuable
 opportunities for practicing professionals to refresh or upgrade
 their skills in quality-based IC design techniques, methodologies
 and tools.  If interested in offering tutorial, please send your
 tutorial proposals to the ISQED tutorial committee to
 widerkehr@isqed.org.  The tutorial proposal should include:

 * Title of Tutorial
 * Name of organizer
 * Name(s), address, and affiliation of the moderator
 * Name(s), address, and affiliation of presenter(s)
 * Half-page summary of each presenter's biography

 You may send your proposal by email as straight text or as an
 Adobe PDF file.  All the presentations must be technical, up to
 date, relevant, and target the design community.  Marketing
 presentations will not be accepted.  It might be helpful to visit
 the archive section on conference web site for a listing of past
 tutorials.  In order to meet the conference time line, we must
 have your complete proposal no later than Sept. 22, 2002.

SUBMISSION OF WORKSHOP PROPOSALS
 Several workshop sessions will be held on the last day of the
 conference.  ISQED workshops are intended to supplement the
 conference by providing in depth, practical and proven design
 solutions for practicing design professionals.  Workshops will be
 taught by experts in the field, who are intimately involved with
 the issues and solutions in their perspective areas, from both the
 industry and academia.  Please send your proposals to the ISQED
 workshop committee to widerkehr@isqed.org.  The workshop proposal
 should include:

 * Title of Workshop
 * Name(s), address, and affiliation of the moderator
 * Name(s), address, and affiliation of presenter(s)
 * Half-page summary of each presenter's biography

 You may send your proposal by email as straight text or as an
 Adobe PDF file.  All workshop presentations must be technical, up
 to date, relevant, and target the design community.  Marketing
 presentations will not be accepted.  It is helpful to visit the
 archive section on conference web site for a listing of past
 workshops.  In order to meet the conference timeline, we must have
 your proposal no later than Sept. 22, 2002.

ABOUT ISQED
 The International Symposium on Quality Electronic Design (ISQED),
 is a premier Design & Design Automation conference, aimed at
 bridging the gap between and integration of, electronic design
 tools and processes, integrated circuit technologies, processes &
 manufacturing, to achieve design quality.  The conference provides
 a forum to present and exchange ideas and to promote the research,
 development, and application of design techniques & methods,
 design processes, and EDA design methodologies and tools that
 address issues which impact the quality of the realization of
 designs into physical integrated circuits.  The conference
 attendees are primarily designers of the VLSI circuits & systems
 (IP & SoC), those involved in the research, development, and
 application of EDA/CAD Tools & design flows, process/device
 technologists, and semiconductor manufacturing specialists
 including equipment vendors.  ISQED emphasizes a holistic approach
 toward design quality and intends to highlight! and accelerate
 cooperation among the IC Design, EDA, Semiconductor Process
 Technology and Manufacturing communities.

 For further information please visit the conference web site at
 http://www.isqed.org.  All inquiries should be addressed to
 isqed@isqed.org