Fourth International Symposium On
High-Performance Computer
Architecture (HPCA)

HPCA-4 Final Program

Sponsor: IEEE Computer Society Technical Committee on Computer Architecture

January 31 - February 4, 1998

Orleans Hotel, Las Vegas, USA

PROGRAM COMMITTEE

ORGANIZING COMMITTEE:

 
CONFERENCE and WORKSHOP SCHEDULE

January 31 (Saturday) 8:00 am - 5:00 pm
Workshop 1:
Fourth Annual Workshop on Computer Architecture Education (WCAE-4)

Organiser: Prof. David Kaeli (Northeastern University)

The goal of the workshop is to provide a forum for educators to discuss and share their experiences and teaching philosophy. The hope is that participants come away from the workshop with a fresh look at how they deliver courses in the areas related to Computer Architecture. This year's workshop addresses a range of subjects in Computer Architecture education. Topics of interest include: Teaching experiences Textbooks, Software Tools, Simulators, Prototyping, Visualization aids, VLSI design packages, Related topics.

 
January 31 (Saturday) 12:00 pm - 5:00 pm
Workshop 2:
Multi-Threaded Execution, Architecture and Compilation (MTEAC 98)

Organisers: W. Najjar and W. Bohm (Colorado State University)

Multithreaded execution is becoming a very important execution model in modern computers, both single and multi-processors. The focus of this workshop is on multithreading execution techniques and systems, including the architecture design and implementation, compilation techniques, system and language support and performance evaluation.

 

January 31 (Saturday) 12:00 pm - 5:00 pm
Workshop 3:
Communication, Architecture, and Applications for Network-based Parallel Computing (CANPC '98)

Organizers: Dhabaleswar K. Panda (Ohio State University) and Craig B. Stunkel (IBM T.J. Watson)

The goal of this workshop is to bring together researchers and practitioners working in the areas of communication, architecture, and applications to discuss state-of-the-art solutions as well as future trends for designing cost-effective network-based parallel computing systems. Topics of interest include: architectural support for achieving fast communication and synchronization, network interface design; implementation of efficient messaging layers; LAN interconnection with high-speed switches and routing; characterization of communication and synchronization traffic; collective communication support in both software and hardware; experience in implementing MPI and HPF; supporting shared memory paradigms; characterizing communication and synchronization requirements in applications; emerging network-based parallel computing applications; interplay between hardware/software support and application characteristics; and performance evaluation and benchmarking. The advance program for the workshop can be obtained by visiting http://www.cis.ohio-state.edu/~canpc98/ or sending an e-mail to canpc98@cis.ohio-state.edu.

 
 
February 1 (Sunday) 8:00 am - 5:00 pm
Workshop 4:
First Workshop on Computer Architecture Evaluation using Commercial Workloads

Organisers : Russell Clapp (Intel Corporation), Ashwini Nanda (IBM T. J. Watson Research Center), and Josep Torrellas (University of Illinois at Urbana-Champaign)

The goal of this workshop is to bring together researchers and practitioners in computer architecture and performance analysis from industry and academia to discuss work-in-progress that utilizes commercial workloads for the evaluation of computer architectures. Also, there will be discussion on the difficulties associated with using commercial workloads to drive new computer architecture designs, including the lack of academic access to database kernel source, and what can be done to overcome these problems. The workshop program will include several invited talks from experts in the field, and a set of talks selected from solicited submissions. The topics covered in the workshop will include characterization of commercial workload behavior, hardware design trade-off analysis using commercial workloads, parallelism and multiprocessing issues, comparison of commercial workload behavior to scientific workload behavior, comparison of end-user workloads to industry standard benchmarks, simulation techniques for predicting the performance of commercial workloads, and application and/or OS kernel algorithm improvements to enhance performance.

February 1 (Sunday) 8:00 am - 5:00 pm
Workshop 2 and 3 Continuation

February 2 (MONDAY)

9:00 am - 9:10 am
Opening Remarks
Kai Hwang
Jean-Loup Baer

9:10 am - 10:30 am Keynote Speech # 1
Database Technology : What's Coming Next?
Phil Bernstein (Microsoft)

10:30 am - 11:00 am -- Coffee Break

11:00 am - 12:30 pm
Session IA : Multithreading
Chair: Josep Torrellas (University of Illinois)

The potential for using thread-level data speculation to facilitate automatic parallelization
J.Gregory Steffan and Todd Mowry (Carnegie Mellon University)

Control Speculation in Multithreaded Processors through Dynamic Loop Detection
Jordi Tubella and Antonio Gonzalez (University of Catalunya, Spain)

Performance study of a Concurrent Multithreaded Processor
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, and Pen-Chung Yew (University of Illinois and University of Minnesota) 

11:00 am - 12:30 pm
Session IB: Routing and Communication Mechanisms
Chair: Dhabaleswar Panda (Ohio State University)

The sensitivity of communication mechanisms to bandwidth and latency
Frederic Chong, Rajeev Barua, Fredrik Dahlgren, John Kubiatowicz and Anant Agarwal (University of California at Davis, MIT, and Chalmers University, Sweden)

Credit-Flow-Controlled ATM for MP Interconnection:
the ATLAS I Single-Chip ATM Switch
Manolis Katevenis, Dimitrios Serpanos and Emmanuel Spyridakis (FORTH and University of Crete, Greece)

A Very Efficient Distributed Deadlock Detection Mechanism for Wormhole Networks
P. Lopez, J.M. Martinez and J. Duato (Universidad Politecnica de Valencia, Spain) 

12:30 pm - 2:00 pm -- Lunch Break

2:00 pm - 3:30 pm -- Session IIA.
Communication Impact on Application Performance
Chair: Lawrence Rauchwerger (Texas A&M)

Challenging applications on fast networks
Koen Langendoen, Rutger Hofman and Henri Bal (Vrije Universiteit, The Netherlands)

Architectural implications of a family of irregular applications
Dave O'Hallaron, Jonathan Shewchuk, and Thomas Gross (Carnegie Mellon University)

The Architectural Costs of Streaming I/O: A Comparison
of worksations clusters and SMPs
Remzi H. Arpaci-Dusseau, Andrea C. Arpaci-Dusseau, David E. Culler, Joseph M. Hellerstein, and David A. Patterson (University of California Berkeley) 

2:00 pm - 3:30 pm -- Session IIB.
SMP Clusters
Chair: Todd Mowry (Carnegie Mellon University)

The Effectiveness of SRAM Network caches in Clustered DSM's
Adrian Moga and Michel Dubois (University of Southern California)

Home-based SVM protocols for SMP clusters: Design and Performance,
Rudrajit Samanta, Angelos Bilas, Liviu Iftode, and Jaswinder Pal Singh (Princeton University)

Fine-grain Software Distributed Shared memory on SMP clusters
Daniel Scales, Kourosh Gharachorloo and Anshu Aggarwal (DEC Western Research Laboratory) 

3:30 pm - 4:00 pm -- Coffee Break


4:00 pm - 5:30 pm -- Panel Session

The emergence of workstation clusters:
Should we continue to build MPPs?

Moderator: Dhabaleswar Panda (Ohio State University)  

Workstation clusters with modern interconnection technologies (such as Myrinet, Fast Ethernet, ATM, Fibre Channel) have gained popularity as a platform for cost-effective parallel processing. As this trend continues to march ahead successfully, more and more architects, system designers and application developers are migrating towards workstation clusters. This leads to the following questions for the parallel processing community.

• Will the demand for MPP systems continue to decline?
• Are there special classes of applications which will need MPP systems in spite of the availability of high performance workstation clusters?
• Are there special QoS issues which will continue to keep the market alive for MPPs?
• Will the MPP systems become obsolete soon?
• Should we target our future research towards MPPs, Workstation Clusters, or both.  
  

Panelists:

• Andrew Chien (University of Illinois),
• Alan Cox (Rice University),
• David Greenberg (Sandia National Lab.)
• Bob Horst (Tandem Computers),
• Steve Scott (Cray),
• J. P. Singh (Princeton University),
• Craig Stunkel (IBM T.J. Watson Research Center)  
  

The panelists will provide their view points and debate on the above questions. 

6:30 pm - 9:00 pm -- Conference Reception

February 3 (Tuesday)

9:00 am - 10:00 am -- Keynote Speech # 2

"Tomorrow's Computing Engines"
Bill Dally (Stanford University)

10:00 am - 10:30 am -- Coffee Break

10:30 am - 12:00 pm -- Session IIIA.
Shared-Memory Multiprocessors
Chair: Pen Yew (University of Minnesota)

PRISM: An Integrated Architecture for Scalable Shared Memory
Kattamuri Ekanadham, Beng-Hong Lim, Pratap Pattnaik, and Marc Snir (IBM T.J. Watson Research Center)

Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma
Sujoy Basu and Josep Torrellas (University of Illinois)

Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas (University of Illinois and Texas A&M University) 

10:30 am - 12:00 pm -- Session IIIB.
Speculation and Register Renaming
Chair: Manolis Katevenis (FORTH, Greece)  

Virtual-Physical Registers
Antonio Gonzalez, Jose Gonzalez, and Mateo Valero (University of Catalunya, Spain)

Supporting highly-speculative execution via adaptive branch trees
Tien-Fu Chen (National Chung Cheng University, Taiwan)

Speculative Versioning Cache
Sridhar Gopal, T. N. Vijaykumar, James E. Smith, and Gurindar S. Sohi (University of Wisconsin-Madison) 

12:00 pm - 2:00 pm -- Conference Luncheon

2:00 pm - 3:30 pm -- Session IVA.
Network Interface Design
Chair: Steve Scott (Cray)

The Impact of Data Transfer and Buffering Alternatives on Network Interface Design
Shubhendu S. Mukherjee and Mark D. Hill (University of Wisconsin-Madison)

Address Translation Mechanisms In Network Interfaces
Ioannis Schoinas and Mark D. Hill (University of Wisconsin-Madison)

Exploiting Two-Case Delivery for Fast Protected Messaging
Kenneth Mackenzie, John Kubiatowicz, Matthew Frank, Walter Lee, Victor Lee, Anant Agarwal and M. Frans Kaashoek (MIT) 

2:00 pm - 4:00 pm -- Session IVB.
Compiler and Operating System Issues
Chair: Alan Cox (Rice University)

Temporal-based procedure reordering for improved instruction cache performance
John Kalamatianos and David Kaeli (Northeastern University)

Performance evaluation of tiling for the register level
M. Jimenez, J. Llaberia and A. Fernandez (University of Catalunya, Spain)

Treegion Scheduling for Wide Issue Processors
William A. Havanki, Sanjeev Banerjia, and Thomas M. Conte (North Carolina State University)

Communication Across Fault-Containment Firewalls on the SGI Origin
Kaushik Ghosh and Allan Christie (Silicon Graphics) 

4:00 pm - 4:30 pm -- Coffee Break

4:30 pm - 5:30 pm -- TCCA Meeting

February 4 (Wednesday)

9:00 am - 10:00 am -- Keynote Speech # 3
Billions and Billions
Steve Wallach (Centerpoint Venture Partners)

10:00 am - 10:30 am -- Coffee Break

10:30 am - 12:00 pm -- Session VA.
Enhancements for DSM systems
Chair: J. P. Singh (Princeton University)

Efficiently Adapting to Sharing Patterns in Software DSMs
Luis Rodolpho Monnerat and Ricardo Bianchini (University of Rio de Janeiro and Petrobras, Brazil)

Comparative Evaluation of Latency Tolerance Techniques for Software Distributed Shared Memory
Todd C. Mowry, Charles Chan, and Adley Lo (University of Toronto and Carnegie Mellon University)

Using multicast and multithreading to reduce communication in software DSM systems
Evan Speight and John Bennett (Rice University) 

10:30 am - 12:00 pm -- Session VB.
Processor Design and Performance Evaluation
Chair: Shahram Latifi (UN Las Vegas)

FPGA based custom computing machines for irregular problems
David Abramson, Paul Logothetis, Adam Postula and Marcus Randall (Monash University, University of Queensland, and Griffith University, Australia)

Non-Stalling Counter Flow Architecture
Mike Miller, Ken Janik and Shih-Lien Lu (Oregon State University)

Partial sampling with reverse state reconstruction:
A new technique for branch predictor performance estimation
Darren Vengroff and Guang Gao (University of Delaware) 

END OF HPCA-4 CONFERENCE