IEEE Computer Society
Technical Committee on Computer Architecture (TCCA) Newsletter
January 2001

Special Issue on Memory Decoupled Architectures and related issues

PAPERS FROM MEDEA-2000 Workshop (MEmory access DEcoupling for superscalar and multiple issue Architectures)

• Micro-Architectural Miss/Execute Decoupling Amir Roth, Craig B. Zilles, and Gurindar S. Sohi
• A High-Performance, Hierarchical Decoupled Architecture  S. P. Crago, A. Despain, J.-L. Gaudiot, M. Makhija, W. Ro, and A. Srivastava
• Execution Performance of the Scheduled Dataflow Architecture  Joseph Arul
• SMT Possibilities for Decoupled Architecture A. Kudriavtsev and P. Kogge
• Segregated Binary Tree: Decoupling Memory Manager M. Rezaei and R. K. Cytron
• A software strategy to improve cache performance S. Bartolini and C. A. Prete
• High Level Power Analysis for Embedded DSP Software J. Laurent, N. Julien, and E. Martin
• Performance Study of the Filter Data Cache on a Superscalar Processor Architecture J. Sahuquillo, S. Petit, A. Pont, and V. Milutinovic

OTHER INVITED PAPERS

• An Algorithm for the Classification of Coherence Related Overhead in Shared-Bus Shared-Memory Multiprocessors P. Foglia
• SimplePower: A Cycle-Accurate Energy Simulator M. J. Irwin, M. Kandemir, and N. Vijaykrishnan
• HydraScalar: A Multipath-Capable Simulator K. Skadron and P. S. Ahuja

REGULAR CONTRIBUTIONS

• Heterogeneous Distributed Shared Memory on Wide Area Network  W. Shi

Membership in the Technical Committee on Computer Architecture is open to individuals who demonstrate willingness to actively participate in the various activities of the TC. A member/affiliate of the IEEE Computer Society may join the TC. A membership application form is included above.

This electronic version of the TCCA Newsletter is substantially identical to the printed hard copy version. However, certain modifications have been made to make this version suitable for on-line viewing,

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