Technical Activities
Purpose
The Technical Activities Group of TTTC is actively involved in: identifying key topic areas in test technology; initiating corresponding Technical Activity Committees (TACs) to coordinate interactions between experts of each topic area; and monitoring the outcome of these technical activities. These technical exchange forums, which include representation from both industry and academia, help identify the common issues of a given topic area and often have an impact on directions and concentration of effort in research. Currently, TTTC has many active TACs: IDDQ Testing, Manufacturing Test, MCM Testing, Memory Test, Mixed-Signal Testing, On-Line Testing, Software Testing, System Test, Test Economics and Test Synthesis. TTTC TACs are encouraged to:
- initiate appropriate meetings including Workshops and Tutorials
- formulate special sessions or panel sessions for TTTC conferences/symposia
- contribute technical material for publications, and organize special issues or sections
- set up and run Round Tables for IEEE Design & Test of Computers
- develop glossaries of terms (common terminology)
- develop and maintain reference lists of key publications and/or products
- conduct surveys regarding the current status and future needs in their area
- provide a technical focal point for those interested in a topic area
- expand the community of interested individuals and seek international representation from industry and academia prepare a membership data base (mailing lists) establish electronic mail reflectors for discussions among your members
- prepare reviewers' list for publications and conferences/symposia
- provide speakers for conferences/symposia and for the TTTC Speakers Bureau
- identify and initiate standards activities in conjunction with Standards Activities Board
- propose nominations for Computer Society and other awards
- develop funding requirements in conjunction with the TTTC Finance Chair
- provide up-to-date information to the test community via the TTTC Newsletter
Each TAC identifies its area of interest in a statement of scope.
If you are interested in joining a TAC you may directly contact the corresponding TAC Chair. Or, if you would like to be involved in a topic area not covered by the current TACs, please contact one of the Technical Activity Group Vice Chairs Michael Renovell, LIRMM, renovell@lirmm.fr or Krishnendu Chakrabarty, Duke Univ., krish@ee.duke.edu or Group Chair Tony Ambler, University of Texas, ambler@ece.utexas.edu.
TTTC TACs
The present TAs and their current chairs are:
Chair: Ben Bennetts, Bennetts Associates, ben@dft.co.uk
Chair: Vincenzo Piuri, University of Milan, Department of Information Technologies, piuri@elet.polimi.it
Co-Chairs: Magdy Abadir, Motorola, abadir@ibmoto.com and Tony Ambler, University of Texas, ambler@ece.utexas.edu
Scope: To promote the awareness of economic issues in design and test, from device through to board, system, and field test. All aspects that pertain to costs will be covered, including product liability.
Chair: Yervant Zorian, Virage Logic, zorian@viragelogic.com
Scope::
Chair: Michel Renovell, LIRRM, renovell@lirmm.com
Scope::
Chair: Burnie West, NPTest, west@ieee.org
Scope::
Chair: Prab Varma, prab@veritable.com
Scope::
Chair: Manoj Sachdev, University of Waterloo, msachdev@ece.uwaterloo.ca
Scope: To support the development of IDDQ/ISSQ testing of CMOS VLSI device testing by the co-ordination of standards in areas such as instrumentation and fault metrics.
Chair: Yervant Zorian, Virage Logic, zorian@viragelogic.com
Scope: To support the development of infrastructure Intellectual Property for the integration of producible core-based integrated circuits.
Chair: Yervant Zorian, Virage Logic, zorian@viragelogic.com
Scope: All aspects of MCM testing including but not limited to: wafer level and die level test and burn-in; known-good die technology: temporary pressure- based and fixed contact-based carrier test; known-good die testability approaches; mechanical and contactless substrate testing; MCM yield models; ATE for MCM testing; assembled module level test, testability, diagnosis and repair; MCM level BIST; testing printed circuit boards with MCMs.
Chair: Rochit Rajsuman, Advantest America R&D Center, r.rajsuman@advantest.com
Scope:: The primary scope of Memory TAC is testing and reliability of stand-alone and embedded memories. In addition, Memory TAC works together with other Technical Committees such as TC on VLSI within the Computer Society and other societies such as Solid State Circuits Society within the IEEE. The scope of this joint effort expands from fabrication technology, memory design, testing and reliability.
Co-Chairs: Bernard Courtois, TIMA-CMP, Bernard.Courtois@imag.fr and Shawn BLANTON, Carnegie Mellon, Univ., blanton@ece.cmu.edu
Scope::
Chair: Bozena Kaminska, 3rd Millenium Test Solutions, bozena_K@3mts.com
Scope: to promote mixed-signal test activities by encouraging people to participate in conference sessions on this topic, in workshop organization, in recruiting new companies, in standard development, and in publicizing new mixed-signal test techniques via magazines (e.g. D&T magazine) and journals (e.g. IEEE Trans. Circuits & Systems).
Chair: Michael Nicolaidis, TIMA, michael.nicolaidis@imag.fr
Scope: To enable the exploration of the advanced on-line testing techniques by the industry and academia through active collaborations, and stimulate advanced research investigations on directions sensitive to influence the design of next generation reliable electronic systems.
Chair: Iboun Taimiya Sylla, isylla@ti.com
Scope: The purpose of this Technical Activity Committee is to explore and support development of RF Test solutions.
Chair: Ian Harris, University of California Irvine, harris@ics.uci.edu
Scope:
The purpose of this Technical Activity Committee is to provide a focal point for ongoing research in the area of System Test. To this end, we perform the following tasks:
- Encourage research in System Test by sponsoring activities at conferences and workshops.
- Provide an archive of information on System Test research.
Chair: Sule Ozev, Duke University, sule@ee.duke.edu
Scope::
Chair: Yervant Zorian, Virage Logic, zorian@viragelogic.com
Scope::
Chair: K.T. Tim Cheng, Univ. of California at Santa Barbara, timcheng@ece.ucsb.edu
Scope: All aspects of test synthesis including but not limited to:
defining high-level testability requirements, measuring testability at
high-level, technology- independent test synthesis, synthesis of self-test
circuitry, performance-driven test synthesis and links to layout, logic or
behaviour-level optimisation, tools to support test synthesis (DfT rule
checking, re-timing optimization, insertion of test structures, hierarchical
ATPG and fault simulation, integration with design synthesis, etc.).
Web Page for
ITC99 Benchmarks
Co-Chairs: Bernard Courtois, TIMA-CMP, Bernard.Courtois@imag.fr and Marta Rencz, rencz@eet.bme.hu
Scope::
Co-Chairs: Magdy S. Abadir, Motorola, abadir@ibmmoto.com and Sujit Dey, Un. of California at San Diego, dey@ece.ucsd.edu
Scope::