This technical area has been active with test community for over 30 years. Memory devices have traditionally been used as test vehicles for new technology, process monitoring and even design concepts. To provide a semi-formal forum to technologists and practitioners Memory Test TAC initiated an international workshop in 1993. This annual workshop, IEEE International Workshop on Memory Technology, Design and Testing is held annually during summer [1]. The 2002 workshop is scheduled on July 10-12, in Bendor, France and in 2003 it will be held in San Jose, CA.

The primary scope of Memory TAC is testing and reliability of stand-alone and embedded memories. In addition, Memory TAC works together with other Technical Committees such as TC on VLSI within the Computer Society and other societies such as Solid State Circuits Society within the IEEE. This cooperation is reflected on MTDT, the scope of which expands from fabrication technology, memory design, testing and reliability. However, Memory TAC within TTTC primarily encourages testing and reliability aspects.

Testing of embedded memories has become one of the most important topics in last couple of years. The main problem is that multi-mega bits memory takes large test time on logic testers, on top of that the direct access to the memory itself is not available. The hardware overhead and performance penalty restricts the use of built-in self-test.

As embedded memories and standard components have different testing requirements. Since 1998, International Test Conference (ITC) has also recognized to address them separately. To properly cover this topic, each year two separate sessions have been devoted to memory testing, one on test generation and algorithm and other on embedded memories. In June 2001, IEEE Design and Test of Computers has also published an special issue on this topic.

Other major test topics encouraged by this TAC are:

Testing for commercial and space applications

What are the best test algorithms, the associated cost

How can a test algorithm be implemented on desktop and on tester to generate the patterns

What are available built-in self-test methods, their associated costs and benefits

Memory redundancy analysis and Built-in self-repair methods

Application of any particular test method, failure analysis and repair method

How to choose a memory test method for a given situation

How to predict storage and life-time reliability