Test Technology Newsletter
October -- December, 1998
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society
TTTC elevated to Technical Council
It is my pleasure to inform TTTC members that, effective immediately, the Computer Society has elevated TTTC to the TEST TECHNOLOGY TECHNICAL COUNCIL.
The IEEE Computer Society Board of Governors at its last meeting voted to raise TTTC from technical committee to technical council in recognition of its many contributions to the test and design communities. For years the Society has sponsored as many as 36 Technical Committees, but only one Technical Council, namely Software Engineering. Meanwhile, thanks to your efforts, TTTC has maintained a high degree of technical, managerial, and administrative excellence in organizing and supporting a numerous and growing number of technical activity committees, conferences, workshops, symposia, standards and tutorials in both emerging and established areas of electronic testing. Through its diverse activities, TTTC provides valuable services to its members and enables their professional growth and technical prowess.
The efforts of many TTTC volunteers made this special recognition happen. As a Computer Society Technical Council, TTTC will be in an even better position to continue its growth and coverage of many subspecialties, while maintaining itself as a single interface point for technical activities for test professionals in all specialty areas as well as in the main test knowledge base.
My wholehearted thanks and congratulations to the many TTTC volunteers who have made this happen.
Yervant Zorian, Chair, Test Technology Technical Council
IEEE Emanuel R. Piore Award
The 1998 IEEE Emanuel R. Piore Award was presented to Janak H. Patel on October 20, 1998 at the Plenary Session of 1998 International Test Conference in Washington, DC. Dr. Patel, a TTTC member, was honored for his contributions to test generation and computer architecture.
Janak H. Patel is currently a Professor of Electrical and Computer Engineering in the University of Illinois at Urbana-Champaign, where he also serves as Co-Director of the Center of Reliable and High-performance Computing. He presently heads a research group dealing with test generation, design for test, and diagnosis for semiconductor chips.
Dr. Patel has been a key contributor to major new advances in test automation and design for test, as well as computer architecture. He began his research in 1971 with the Electronics Research Laboratory of Stanford University, performing diagnosis and repair of mini-computers. In 1972 he became a research assistant on pipeline computing while obtaining his Ph.D. at the university.
After obtaining his degree, Dr. Patel joined the faculty of School of Electrical Engineering at Purdue University where he started research on fast asynchronous switches that connect many processors and memories. He later moved to the University of Illinois where he continued research in the field of Computer Architecture, with an emphasis on design and analysis of multi-processor cache memories.
In 1986 he became a founding technical advisor to Nexgen Microsystems in San Jose, California, focusing on cache designs. In 1990 he co-founded Sunrise Test Systems in Sunnyvale, California to productize his research at Illinois. During 1990-91, Dr. Patel served as Vice-President of R&D at Sunrise Test Systems, where he still continues as a technical consultant.
Dr. Patel has pioneered several new techniques in computer architecture. His work on delay insertion in pipelines inspired software scheduling in compilers of super-scalar microprocessors and large vector processors. His work on interconnection networks, called Delta Networks, is recognized as a foundation block in the field of analysis of high-speed switching networks in the communications industry. Several commercial multiprocessor designs use his invention of a cost-effective solution for ensuring data consistency in cache memories. He developed a method of cache simulation that requires only a small fraction of the time and storage needed by more conventional methods.
Janak Patel was born in Bhavnagar, Gujarat, India on May 29, 1948. He obtained a B.Sc. degree in Physics from Gujarat University in 1967. He went on to receive a B.Tech. degree from Indian Institute of Technology, Madras, in 1970. In 1971 and 1976 he received his M.S. and Ph.D., respectively, at Stanford University in Electrical Engineering.
Dr. Patel, an IEEE Fellow, holds a patent on automatic test generation and has published over 150 professional papers. He was a recipient of the Best Paper award at the 1998 VLSI Test Symposium. He has made a number of Keynote and Distinguished Lecture presentations to industry and academia. Patel has been a participant in TTTC-sponsored technical meetings since 1987 and has served on the program committees of VLSI Test Symposium and International Test Synthesis Workshop.
The Piore Award honors the memory of Emanuel Piore, an enlightened American Scientist who understood the value of basic research, as well as that of applied research. The award, established in 1976, recognizes achievement in the field of information processing that contributes to advancement of science and the betterment of society. Sponsored by IBM, the award includes a bronze medal, certificate, and cash honorarium. Past recipients for the years 1990-1997 are: Allen Newell, Joseph F. Traub, Harold S. Stone, Makoto Nagao, John L. Hennessy, Yale N. Patt, Edward J. McCluskey, and Shun-Ichi Amari.
From information supplied by IEEE and TTTC
Reminiscing about TTTC
This is my last issue as TTTC Newsletter editor, another milestone in my long association with TTTC. It has been quite a trip.
In 1983, as TTTC Chair, I was first exposed to the efforts required to publish the TTTC Newsletter. Five newsletter issues were published the previous year under the chairmanship of John Bauer and editors Rod Tulloss and Kovi Kovijanic. In 1983, we struggled to publish three issues. Mark Harrison, who replaced Rod as editor, and I continued the established practice of publishing one or two technical articles on test, plus the usual news of TTTC activities. A couple of years later TTTC decided to drop that practice because authors wanted to publish in journals where they would receive more recognition. That decision gave the NL less material to publish. In the late 80's, the newsletter languished when companies reduced or even eliminated support for professional volunteers and even less material to publish was available. In 1990, Don Lenhert became editor and revived the publication. I became involved again, first as publisher and then, in 1992, as editor. The difficulties in getting articles have continued. Last year, we tried to publish six issues, but the lack of submitted material forced us to cut back to quarterly issues last January.
Lately, however, there seems to be a resurgence. Due to the burgeoning of TTTC activities and the strong efforts of Yervant Zorian in soliciting articles, this edition and the last one have been rich and full of articles. We are getting plenty of submissions, although well past our scheduled deadlines. We hope that the impetus Yervant has given the newsletter will result in momentum that will propel it forward in 1999 and into the new millennium under a new editor.
I started my association with the professional test community in 1972 when Tudor Finch, an active leader in test in those days and my department head at Bell Labs, sent me to the Cherry Hill Test Conference, which later became ITC. Later, I joined the ITC Program Committee and in 1980, I became ITC Chairman. In the meantime Ned Kornfield and Ken Anderson started TTTC when the Computer Society began organizing technical committees.
Those were exciting years. ITC was growing rapidly. and TTTC began its sponsoring of workshops. In the early 80's ITC spun off several workshops. Among these early workshops, Tom Williams' DFT and European DFT Workshops, Rich Sedmak's BIST Workshop, Don Scharfetter's Napa Valley Workshop, Jerry Kunert's ATPG Workshop, and Kunert's VLSI Test Workshop, which became VLSI Test Symposium, come to mind. ITC wanted workshops in the Spring to generate papers and sessions for its expanding Fall conference. Over the years, the TTTC/ITC workshop efforts have been very successful. This year, TTTC sponsored 28 meetings on three continents, many of them traceable to the ITC connection.
Doris and I have been semi-retired for about a year now. We have found semi-retirement so enjoyable that we gleefully anticipate the completion of the retirement process, but we will miss the opportunities to meet with our many TTTC and ITC friends.
We sincerely hope that TTTC and the Newsletter will prosper and we wish the new editor the best.
I will be available on e-mail if anyone wishes to chat. But don't expect an immediate reply. I may be travelling, biking, trying to make my photographic prints look the same as the photos on my monitor, or loafing.
Ed Thomas
Test Technology Educational Program for 1999
The TTTC Tutorial Group has initiated a Test Technology Educational Program. Through this program TTTC plans to offer one-day tutorials on state-of-the-art topics in test. The program will provide an opportunity for design and test professionals to update their knowledge base in test.
The tutorials will be held in conjunction with TTTC-sponsored technical conferences such as ITC, VTS, ATS, ETW, etc. A program committee will review the proposals and develop an annual TTTC educational program. For more information on this program contact the Tutorials Group Chair Michael Nicolaidis michael.nicolaidis@imag.fr or Joan Figueras figueras@eel.upc.es.
As part of the program the Tutorials Group invites tutorial proposals for the following technical meetings. Proposals for these meetings must be submitted by February 1, 1999.
Meeting Location Dates
ETW'99 Constance, Germany May 25, 1999
ITC'99 Atlantic City, NJ, USA Sep 25-27, 1999
DFT'99 Albuquerque, NM, USA Oct 31, 1999
ATS'99 Shanghai, China Nov 16, 1999
If you are interested in presenting a tutorial at one or more of these meetings, please send a proposal by e-mail to Joan Figueras. Include the following information:
1.
The technical meeting(s) where you wish to present the proposed tutorial(s). If
you select more than one meeting, indicate your priority.
2. Title of the proposed tutorial.
3. Names, affiliations, e-mail addresses, telephone
and fax numbers, and postal addresses of all presenters. Indicate the contact
person.
4. The intended audience for the proposed tutorial
in approximately 30 words.
5. A concise summary of the proposed tutorial in approximately
100 words.
6. A detailed description of the tutorial in 2000
words or less indicating the topics that will be covered and the presentation
time that each of the topics will require.
7. A bibliography of your source material.
8. A description of any support material you expect
to distribute to attendees, e.g., textbook, copies of slides/foils, etc.
9. Short biographical sketches of 500 words or less
for all presenters. In addition to educational and professional achievements,
include any previous experience in presenting tutorials and any other
information which could aid reviewers in assessing the presenters presentation abilities
and expertise in the tutorial topic.
Sreejit Chakravarty
TTTC's Latin American Group reports 1st year progress
From its creation in September 1997, the Latin American Group of TTTC (LA-TTTC) has grown to 44 members in six countries. Fabian Vargas, Catholic University, Porto Alegre, Brazil, chairs the group. Vargas is assisted by Vice Chair Victor H. Champac, Instituto Nacional de Astrofisica, Puebla, Mexico. In its first year of existence, LA-TTTC has established an Internet homepage, initiated a number of projects, and plans to hold a technical meeting tentatively titled the 1st IEEE Latin-American Workshop on Test and Defect Tolerance.
Interested TTTC members and others can learn more about the group's projects on their homepage at: http://www.epo.pucrs.br/ee/ppgee/tttc-la.html. The site has short summaries of cooperative undertakings between group members and local industry, a group member list and a link to the TTTC homepage. The member list has links to members' personal homepages. Currently under construction at the homepage is a section containing tutorials on the basics of test, defect tolerance, and related topics.
The LA-TTTC group is in the process of appointing an Industry Liaison and an Awards Vice Chair who will work with the TTTC Awards Committee.
The group held its first open meeting in Buzios, Rio de Janeiro, Brazil, during the XI Symposium on Integrated Circuit and System Design. About 20 persons, mostly from Brazil, Argentina and Mexico, attended. After presenting the structure and purpose of LA-TTTC, the meeting organizers emphasized the benefits of being a member of the LA-TTTC Group. The audience asked what effective ways the group could use to serve LA-TTTC members and the testing community, taking into account the fact that LA-TTTC is a small group and most members come from academia. The idea of organizing a workshop on test and defect tolerance was presented during the meeting and discussed with the audience. Part of the audience believes that most LA-TTTC members work in test rather than fault tolerance. However, it is important to attract the fault tolerance people to work with the group in workshop organization. The incorporation of "Defect Tolerance" in the title and in the topics covered by the workshop is an effective way of doing this. Several persons from France expressed interest in connecting with LA-TTTC and asked to subscribe to the LA-TTTC e-mail list.
In conclusion: LA-TTTC is a young organization working towards consolidation. The planned workshop, an important vehicle for carrying the group forward, will encourage members from different communities to work together and to exchange valuable experiences.
From a report by Fabian Vargas, vargas@ee.pucrs.br
Bare Substrate/Board Test
As interconnection densities of bare substrates continue rising, so does the cost of advanced electrical testing. Today, investing in a new test facility has become one of the most strategic decisions for a substrate manufacturer as well as for their system house customers.
During the MCM Test V Workshop in Napa, Yervant Zorian, Ara Talaslian and Bernard Courtois suggested the creation of a new TAC to address bare substrate test. They initiated the setup of a new TAC chaired by Christophe Vaucher, who has 9 years experience in the electrical test of bare substrates. The Bare Substrate/Board Test TAC will focus on the electrical test of advanced substrates such as MCM, Printed Circuit Boards, etc.
The committee is currently taking its first steps. Vaucher is putting together a session dedicated to bare-substrate-level test for the 1999 High Density Module Test VI Workshop. The TAC is preparing a bare substrate test report that will present the main issues of bare-substrate test and disclose current developments in the field. The report will be made available in January 1999. The committee is also developing a glossary of terms for the field. During this first year the TAC also will try to determine if there is a significant interest in this activity, and to define directions the committee should take.
The new TAC asks that you send your inquiries and suggestions to: Christophe.Vaucher@bare-board-test.com
Tel: + 33 494 25 02 02. Fax: +33 494 25 07 54
C. Vaucher, Chair, Bare Substrate/Board Test TAC
On September 14, 1998, the Test Community lost one of it's very good friends when Robert Cogné passed away. Monsieur Cogné received his engineering education at the prestigious, Ecole Normale Superieure in Paris. Following his degree work he became an officer in the Navy of France, serving in the Pacific area. Later he joined ITT in France as an engineer, eventually rising to a senior executive position. Cogné was responsible for all test activities in ITT and its European subsidiaries. After retiring from ITT, he continued his professional activities as a consultant. Among other work, Cogné advised the countries of Vietnam and China in improving their technical infrastructures.
In the late 1970's, Cogné was active in the IEEE Computer Society's International Test Conference as its European representative. He soon became the driving force behind the establishment of professional activities in the area of test in Europe. In the early 1980s, following his contacts with the Design For Testability Workshop held in Colorado, he recognized that there was more than enough good DFT work in Europe to support a similar activity. Subsequently he initiated the establishment of the European Design For Testability Workshop, perhaps the earliest test activity in Europe sponsored by the Computer Society. After this success he was a founder and the first Chair of the IEEE Computer Society's European Test Conference which has evolved into a key division of the DATE (Design, Automation and Test in Europe) Conference series.
Robert Cogné, a wise and respected man of vision, always had time to talk and to help the novice in test as well as the seasoned professional. Many of us will miss him, a dear friend and valued colleague.
Thomas W. Williams, Synopsys, Inc., USA, and Joachim P. Mucha, University of Hanover, Germany
NEW TTTC MEMBERSHIP BOOTH DEBUTS AT ITC'98
The Test Technology Technical Committee introduced a new, interactive membership booth at ITC this year. Located in the ITC registration area, the booth was manned by Maddie and Alex Harwood of the TTTC Office, the TTTC Executive Committee and other TTTC volunteers. The new booth elicited a tremendous amount of interest from ITC participants.
In the past, TTTC furnished a literature table for distribution of various workshops' Calls for Papers and Calls for Participation, but there was no one at the table to provide information or answer questions. The 1998 TTTC membership booth, complete with graphics, posters and a TTTC Banner, included a membership brochure outlining the benefits of TTTC membership, TAC brochures describing each Technical Activity Committee, membership applications, samples of the TTTC Newsletter, a 1998 TTTC Monthly Planner, and notepad give-a-ways, as well as literature on the numerous TTTC-sponsored workshops.
Many participants expressed interest in TTTC membership, as well as surprise at the level of activities and events in which TTTC is involved. Many were unaware that TTTC sponsored 28 technical conferences, symposia and workshops this year, of which ITC is one; or that there are 18 different Technical Activity Committees.
As a result of this year's TTTC booth participation at ITC, we distributed hundreds of membership brochures, TAC informational brochures and other literature, and acquired more than 160 new members.
Article by Maddie Harwood
TTTC members receive service awards at ITC'98
Each year the IEEE Computer Society and TTTC honor and recognize members who have given outstanding service in furthering the goals of TTTC and the Society. This year, the Society and TTTC presented the following IEEE Computer Society awards at ceremonies conducted during the Awards Banquet of ITC Test WeekTM. TTTC sincerely congratulates all of the awardees for their accomplishments.
MERITORIOUS SERVICE AWARD
William C. Bruce - For providing skilled management and technical guidance to the IEEE International Test Conference over many years.
OUTSTANDING CONTRIBUTION AWARD
Rabrindra K. Roy - For providing leadership and guidance over numerous years to the emerging VLSI Test Symposium.
William R. Mann - For founding and leading the Southwest Test Workshop.
CERTIFICATE OF APPRECIATION
R. G. Ben Bennetts - For successfully chairing the Program Committee of the IEEE International Test Conference 1997.
Kwang-Ting Cheng - For serving as Chair for ITSW'97 and TS TAC
Patrick Dewilde - For serving as General Chair for the first Design, Automation, and Test in Europe (DATE) Conference in Paris, 1998
Joan Figueras - For successfully running the European Test Workshop for one year
Hans Kerkhoff - For successfully organizing and chairing the 4th IEEE International Mixed Signal Testing Workshop in The Hagues, 1998
Donald H. Lenhert - For significant contributions as webmaster of TTTC and coordinator for D&T Newsletter for the last several years
Fabrizio Lombardi - For serving as the Chair for the Memory Technology, Design and Testing Workshop for 1997 and 1998
Edward J. McCluskey - For serving as General Chair for the Northwest Test Workshop for the last several years
Michael Nicolaidis - For serving the TTTC as Chair of its Technical Activities Group
Paolo Prinetto - For very successfully serving the TTTC, as Chair of its European Group (ETTTC) from 1994 to 1997
Rochit Rajsuman - For serving as Chair of the Memory Test TAC for the last several years
Fabian Vargas - For serving as the TTTC Latin American Group Chair for 1997 and 1998
Prab Varma - For running the HLDVT Workshop for several years and for serving as HLDV TAC Chair
Burnell West - For significant contributions to the TTTC Membership Directory
Hans-Joachim Wunderlich - For successfully running the 10th Workshop on Test Methods for Circuits and Systems in Germany (1998)
All of the awards were presented under the auspices of the IEEE Computer Society Awards Program. Any TTTC member who wishes to nominate a person who has contributed to the furthering of TTTC goals should contact Bruce C. Kim, TTTC Awards Chair, E-mail: kimb@egr.msu.edu
Bruce Kim, TTTC Awards Chair
TTTC announces James Beausang DFT Student Award Program
To encourage student participation and recognize excellence in the field of design for testability, the IEEE Computer Society Test Technology Technical Council is pleased to announce that it will sponsor the TTTC James Beausang DFT Student Award Program in 1999 and 2000. The award honors the memory of Dr. James Beausang, a well-known researcher and practitioner in the domains of Design for Testability and Test Synthesis.
The award will be granted twice a year for two years. 1999 and 2000. One award will be presented at ITC and one at VTS in each of these years, recognizing one outstanding student paper at each of these conferences. The awards will be presented during the plenary sessions of the meetings in the same year as the student's conference submission and acceptance.
The award-winning papers will be selected from qualifying papers selected by the ITC and VTS Conference Program Committees. The TTTC James Beausang DFT Student Award Committee will consist of five test experts, namely: Ken Wagner (Chair), Tony Ambler, Ben Bennetts, Denis Martin, and Tom Williams.
At minimum, the award will consist of a $500 check, a certificate of recognition, and complementary registration at a selected TTTC workshop, valid within one year. In addition, the award-winning papers will be published in IEEE Design and Test Magazine.
The award will be granted to undergraduate and graduate students listed as primary authors of eligible papers. The papers may be based on university or industrial work.
The award will be endowed with private, corporate and organization funds. Any excess funds after the award period will revert to the TTTC to be used for activities that benefit students.
TTTC requests student submissions for consideration for awards
Student authors interested in this award should submit papers to ITC or VTS in accordance with the submission requirements of those technical meetings, indicating on the ITC or VTS manuscript submission form or on their submission cover page that award eligibility requirements have been met by adding the phrase, "Please consider this submission for TTTC's James Beausang DFT Student Award Program." Eligible subject areas include: architecture, synthesis and analysis research applied to scan, design for testability, test synthesis, BIST, and boundary scan and embedded core test topics.
Private and corporate donations solicited
TTTC invites private and corporate donations to assist in endowing the student award. Donations to the memorial fund will be received till January 31, 1999. Donations will be tax deductible. To donate to the fund, please write a check to TTTC's James Beausang DFT Student Award Fund and mail it to: TTTC Office, 1474 Freeman Dr, Amissville, VA 20106, USA, Or call +1-540-937-8280, with your credit card number ready. The list of donors will be published in the TTTC Newsletter.
TTTC would like to acknowledge several ex-colleagues of James Beausang including: Tony Ambler, Ben Bennetts, Bryn Ekroot, Chris Ellingham, Denis Martin, Alida Mascittelli, Pete Moceyunas, Slawomir Pilarski, Jim Sproch, Gordon Robinson, Ken Wagner (coordinator), Tom Williams, and Yervant Zorian (coordinator), who have faithfully initiated, specified, and proposed this memorial award.
For further information and updates please check
http://computer.org/tttc or contact Ken Wagner at kenneth.wagner@smi.siemens.com
Ken Wagner
New DFT benchmark effort gets underway
TTTC is sponsoring an initiative to collect a new set of ATPG benchmarks for presentation at the 1999 International Test Conference. The Benchmarks Subcommittee, under the DFT TAC, is collecting a set of realistic benchmark circuits for distribution to DFT researchers around the world.
The goal of this effort is to provide realistic example circuits that will stress current ATPG algorithms, thus providing the impetus for the development of new ATPG and DFT algorithms. A truly successful set of new benchmarks would break current ATPG and DFT tools. Only breaking existing tools will motivate development of better tools and fundamental techniques for dealing with real circuit structures.
The benchmarks, to be collected from industry and academia, will be described at both RTL and gate levels and will include features such as embedded memories, internal busses, and cores, and they will be hierarchical. Lists of gate level stuck-at and transition faults, and subsets of bridging and path-delay faults, will be published. The collection and maintenance of the benchmarks is intended to be a continuing process, with extensions to the benchmarks (such as layouts and realistic defect lists) provided later.
The first set of benchmarks should be available in early 1999. The benchmarks and preliminary results will be presented at a special session of ITC'99.
Why do we need a new set of benchmarks?
The last full set of ATPG benchmarks was released in 1989, almost a decade ago. By providing a common basis for comparing algorithms, they had the effect of jump-starting work on sequential ATPG. However, the old benchmarks (ISCAS'85 and ISCAS'89) have lost their value for a number of reasons: they are at the gate level, they are not hierarchical, they do not include realistic circuit features such as memories, and they are small. They are much too easy in today's world of million-gate designs. Since all of today's ATPGs can handle the ISCAS'89 designs, progress in ATPG algorithms has stalled from lack of a challenge.
What should a new set of benchmarks contain?
At least some should be available at the RTL level. They should contain multiple-clock domains, internal tri-state busses, memories, IOputs, and other things that real world test writers must face. If some were system-on-chip designs, we would be able to compare the effectiveness of the many solutions for embedded core testing being proposed today.
What benefits should we get from new benchmarks?
Though commercial tools can handle almost all designs (assuming the use of full scan) some things are still difficult. Embedded-memory support requires either scanning around the memory (and possibly losing fault coverage for logic inside the scan ring) or modeling the memory, which is difficult and which slows down test generation. Perhaps new university research in memory support would help -- research that is hampered today by a lack of examples. So far there has been little successful work on high-level test generation or DFT. Perhaps published algorithms would work well on large RTL designs. We don't know, since there are none freely available on which to test the algorithms. We believe that freely published and reproducible results will lead to healthy competition between research groups. This would accelerate the discovery of new and better DFT algorithms and techniques.
What can you do to help?
First, visit the Benchmark website at
http://www.cerc.utexas.edu/itc99-benchmarks/bench.html.
There you can subscribe to the benchmark mailing list and view more detail on benchmark requirements and justification. If you are interested in getting the benchmarks, you can fill out a survey so that we better understand your requirements.
What we most need are benchmark circuits. If you are in a design organization, are there any antiquated ASIC designs that can get cleared for distribution? You can change the signal names if you wish. Could you provide a large sub-circuit of an old design? If you work for a CAD company, are there test circuits that you have constructed that could be shared? Could your university donate designs done for class or research projects? Interesting designs do not have to be state-of-the art.
If you are interested in donating a design, there is a form to fill out on the web page. All donations are anonymous.
For more information, please visit the web page or send mail to Scott Davidson, scott.davidson@eng.sun.com.
Scott Davidson
VLSI Test Symposium 1998 celebrates sweet sixteen
In Monterey, California, recently, the IEEE VLSI Test Symposium celebrated a successful sixteenth year, continuing its growth from a small workshop to a leading international forum where many of the world's leading test experts and professionals from both industry and academia join to debate key issues in testing. VTS'98, sponsored by the Computer Society's Test Technology Technical Council, attracted over 285 attendees from both the electronics industry and the world's leading universities.
The complexity of current-generation microelectronic components, combined with rapidly developing high-density packaging and reduced design cycle times, has made it extremely difficult and expensive to comprehensively test electronic systems and diagnose failed parts using established methods. Test experts warn that the situation will only worsen with an increasing number of chips being designed with intellectual property (IP) blocks or cores, both analog and digital, and with high-speed packaging. Clearly, the electronics industry needs innovative advances in test, design-for-test, and diagnosis methodologies in order to match the rapid advances in design technologies, and to minimize costs while delivering high product quality.
The theme of VTS'98: Test Innovations for Highly Complex, High Speed, Deep Sub-micron ICs, reflected these critical demands. A two-and-a-half day technical program aptly addressed these needs in 62 paper presentations, four panel sessions, four embedded tutorials, and five tutorials. A keynote address by Bill Bottoms, Chairman and CEO of Credence Systems Corporation, highlighted the issue of test complexity in the next millennium. Spirited discussions on topics relatively new to VTS such as embedded-core testing, signal integrity in deep sub-micron, RF testing, and design validation, augmented the animated exchanges on scan test, mixed-signal test, delay test, current testing (IDDQ), fault simulation and other more established subjects.
In 1999, the seventeenth VTS will be held at Marriott Laguna Cliffs Resort in Dana Point, California, USA, overlooking the Pacific Ocean and the Southern California coast line. The theme of VTS '99 is Scaling Deeper to Sub-micron: Test Technology Challenges.
For further details regarding VTS '99, please contact: Michael Nicolaidis, General Chair, TIMA, 46 Avenue Felix VIALLET, 38031 Grenoble Cedex, FRANCE. Tel: +33-476-57-4619. FAX: +33-476-47-3814. Email: Michael.Nicolaidis@imag.fr, or Adit Singh, Program Chair, Dept. of Electrical Engineering, Auburn University, Auburn, AL 36849. Tel: +1-334 844-1847. FAX:+1-334-844 -1809. Email: adsingh@eng.auburn.edu
Anand Raghunathan, anand@ccrl.nj.nec.com
Defect and Fault Tolerance Symposium marks 12th year
The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems marked its twelfth annual meeting on November 2-4, 1998, Austin, TX, USA. Beginning in 1986 as the Design for Yield Workshop in Oxford, UK, we progressed from a workshop to a symposium three years ago, but still remain the premier forum for discussion of all aspects of hardware fault tolerance, whether from a circuit yield or test perspective. This year we continued the tradition of bringing together from across North America, Europe and Asia the practical experience of engineers active in manufacturing and the more theoretical approach of academics.
Papers on yield spanned the range from practical defect control in semiconductor manufacture, to the issues of layout from a floor-planning perspective and critical area analysis. From these papers, we gradually moved to higher abstraction levels in the consideration of fault tolerance, with papers dedicated to fault modeling and analysis, and circuit-level fault tolerance, concluding with system-level fault tolerance. For the first time we also had a session dedicated to yield and reliability issues of analog and mixed-signal circuits, stressing the increasing relevance of these topics.
The important issue of next-generation, very-deep sub-micron ICs' reliability was introduced by our keynote speaker, Yervant Zorian, LogicVision, who focused on LogicVision's testing difficulties and derived reliability problems. Then our invited speaker, Michael Nicolaidis, TIMA, discussed the perspectives of hardware fault tolerance as a design strategy to cope with these problems. A panel moderated by Jacob Abraham, University of Texas at Austin, followed the invited presentations. The panel discussed the needs and perspectives of fault tolerance in industrial. Thanks to the provocative and controversial opinions expressed by our moderator and panelists, the panel resulted in a lively open discussion, with many keen protagonists amongst the audience.
As program chairs, we found the many expressions of interest in this year technical program very gratifying. We were also delighted to be told by several attendees that they would return to their employment with a number of fresh approaches gathered at the Symposium: this proved to us that the DFT Symposium continues to serve its primary purpose.
Next year the DFT Symposium will be held in Albuquerque, New Mexico, USA, November 1-3, 1999. For more information on the DFT'98 technical program and the DFT'99 meeting, please consult our web site at:
http://www.ee.ed.ac.uk.dft/
Cecilia Metra and Neil Harrison, DFT'98 Program Co-Chairs
ITC hosts 1st Microprocessor Test and Verification Workshop
The First Microprocessor Test and Verification 1998 Workshop (MTV98) was held October 22-23 in Washington DC, during ITC Test WeekTM. The workshop brought together researchers and practitioners from the fields of verification and test to exchange innovative ideas and to discuss new methodologies to solve the difficult challenges in various processor design environments. The workshop succeeded in providing an environment for cross-fertilizing test and verification experiences and innovative solutions among the 70 or so attendees who participated. These events included a keynote presentation, several paper sessions and an industrial panel.
The contributions covered a wide area dealing with topics such as: experiences in test and validation of high-performance processors, simulation-based design verification, performance testing, high-level test generation for functional verification, formal techniques and their applications, design error models, and verification coverage. A lively panel comprised of highly respected industry experts debated the potential of formal verification to take the lion's share of design verification away from simulation-based methods.
All participants received an informal proceedings of the contributions presented during the workshop. A selection of the papers will be published in a special issue of JETTA to appear in November 1999. A call-for-papers for the special issue has been sent out to all TTTC members by e-mail.
All in all, MTV98 was a success. We plan to hold MTV99 in conjunction with ITC on 10/31-11/1, 1999 in Atlantic City.
For more information about MTV98, MTV99, or the JETTA special please contact abadir@ibmoto.com.
Magdy Abadir
MCM Test V Advanced Technology Workshop 1998 discusses high-density module test problems in Napa Valley
The 1998 Multichip Module Test Advanced Technology Workshop gathered an impressive group of test professionals from industry and academia. The three-day annual event, with the backdrop of California's Napa Valley, has become a tradition among test professionals the world over. Attendees and speakers from across North America, Europe and Asia added to the diversity and richness of the workshop's content.
The traditional informal atmosphere of the workshop, exemplified by a no-tie policy, is conducive to information exchange and networking among attendees, speakers and program committee, and this year was no exception. To further encourage networking, the program committee worked hard to select speakers so that problems raised by one speaker were often addressed by another speaker. A good example of this dynamic was the parallel contacting problem raised by David Keezer of Georgia Tech in his presentation of a high-speed substrate test approach and the possible solution that Karl Zimmermann of CK Technologies proposed in his talk on buckling beam probe technology.
The workshop was structured into five sessions, including a panel session, such that the discussion progressively evolved from theoretical considerations to practical applications. The sessions covered the latest developments in module- and substrate-level test strategies, test equipment, and test applications. Tutorial sessions at the beginning of the module-level and substrate-level test strategy sessions were added this year to promote a more uniform audience understanding of the presentations that followed.
The session on module-level test strategies dealt with the challenges faced by ever-increasing operational speeds and the need for Known-Good Die with the widening appeal of bare die utilization in industry. The presenters addressed the difficulties of testing at-speed within the constraints of propagation delays added by ATE fixturing by proposing methods to move generation of test signals from the ATE closer to the DUT. One method proposed the use of IC buffers between the ATE and the DUT. On the KGD front, a presenter proposed a binning approach, taking advantage of the fact that failures within a wafer occur in a clustered fashion, as a means of screening out potential burn-in failures, without having to actually perform burn-in.
The sessions on substrate-level test strategies and test equipment mainly concentrated on the difficulties of testing substrates at ever-increasing levels of density. This problem is amplified when these high-density substrates must be tested at high production volumes. After an excellent presentation by Christophe Vaucher from the Bare-Board-Test Work Group (France) covering the current general status of substrate test technology, many potential answers to the density and throughput challenges were presented. These ranged from contactless electron-beam technology to flying probes to high-density bed of nails. Hybrid strategies, such as contactless flying probes, were also discussed.
The panel session this year covered the challenges faced when moving from prototype to high-volume production testing. Interesting discussion took place about the choices test professionals face regarding test equipment and test coverage when going to high volume, mainly the cost issues that are involved. KGD (or the lack of KGD) was raised as the main issue for module-level testing, whereas the high cost of investment for dedicated test probes raised particular concern at the substrate level. Panelists and audience engaged in a very open and frank debate regarding the balance that needs to be struck between test coverage and cost.
The MCM Test series of workshops is co-sponsored by IMAPS (International Microelectronics and Packaging Society) and IEEE TTTC. The workshop benefits from the resources of both organizations to expand the scope of subjects from the test of passive substrates to that of complex modules.
Throughout this year's workshop the topics discussed went beyond the boundaries of classical MCM technology and applied to the broader topic of high-density modules. To reflect this trend, the program committee has decided to name the 1999 workshop High-Density Module Test VI. The workshop will be held in Napa Valley, CA, on September 12-15, 1999. The program committee is already hard at work preparing this next event in the series. We hope to see you in Napa next fall.
Ara Talaslian, IBM Microelectronics, Program Chair. atalasli@email.msn.com
TECS Workshop moving to California
IEEE P1500, TTTC Embedded-Core Test Tutorials, D&T Magazine special issue on core-based systems, ITC Special Track on Core Test, and SOC test panel sessions -- these are a few examples of the technical activities initiated by the TTTC TAC on Embedded-Core Test that are attracting the test community to one of the most challenging problems of today's IC technology: test reuse of IP cores.
Perhaps the most intensive of these initiatives is TECS, a workshop introduced in 1997 fully dedicated to embedded-core test. TECS, formally known as the International Workshop on Testing Embedded Core-based System-Chips, attracted excellent technical papers and a record number of attendees (235) for a first time workshop. TECS 97, held during ITC Test WeekTM '97, was sponsored by TTTC, in collaboration with the Virtual Socket Interface Alliance (VSIA).
TECS 98, held in Washington, D.C., during ITC Test Week'98, brought together core providers, integrators, and manufacturers in an informal forum for presenting and discussing new developments in testing such systems. An invited talk on the market for system-on-chip testing, by R. Puhakka, VLSI Research, initiated the workshop. Paper sessions were dedicated to current practices in SOC test, new approaches in testing embedded cores, experiences in testing reusable core-based systems and Philips' approach to core test. The program also featured invited presentation son the IEEE P1500 standardization effort.
Since TECs opportunity to be held for two years at ITC was completed, the TECS workshop committee decided to move to a new venue and season. Emulating VTS's successful move to California, TECS 99 will reconvene in conjunction with VTS 99 at the Marriott Laguna Cliffs Resort in Dana Point, California, USA, April 28-29, 1999.
If you are engaged in the most up-to-date work in this field, please submit a paper proposal by January 15, 1999 to TECS 99. Send your postscript submissions (extended summary or full paper) or information requests to:
Yervant Zorian, LogicVision Inc., Workshop Chair, zorian@logicvision.com
International Test Conference 1999
International Test Conference, well-known to TTTC members as the world's premier conference on electronic test technology, covers the complete test cycle from design verification, test, diagnosis, failure analysis, and back to process and design improvement. The 1999 conference has adopted the theme Test and the Product Life-Cycle. At ITC, test and design professionals can confront the challenges the industry faces and learn how these challenges have been addressed by the combined efforts of academia, design tool and equipment suppliers, designers and test engineers. The 1999 conference will be held September 28-30, 1999 at the New Atlantic City Convention Center, Atlantic City, NJ, USA.
In 1999, ITC will supplement its usual broad coverage of topics by devoting added resources to board test and system test, including a special seminar and/or paper track.
ITC, the cornerstone of Test WeekTM, offers a wide variety of technical activities targeted at test and design theoreticians and practitioners, including: formal paper sessions, tutorials, panel sessions, case studies, commercial exhibits and presentations, and a host of professional meetings.
Authors are invited to submit original, unpublished papers describing recent work in the field of test and design. For submission requirements and a list of topics, please visit the ITC Web site: http://www.itctestweek.org
ITC maintains a highly competitive selection process for papers presented. For details of the selection process, please consult the current publications of the ITC Proceedings, or call the ITC office. Submissions must clearly describe the status of your work, its significance, and highlights. Supporting data, results and conclusions, and references to prior work must also be included. ITC does not accept submissions that do not meet all specified criteria.
Submission deadline: FEBRUARY 12, 1999
Author Notification: May 7, 1999
Manuscript deadline: July 9, 19998
Proposals for Panels, Informal Sessions, Lecture Series, Tutorials and Workshops are also welcome.
For 1999, ITC will use electronic submission. E-mail your paper proposal to itc99papers@courtesyassoc.com. Do not fax your submission.
FTP submission is also available. For direct submission of a paper or panel, register and submit your proposal.
For further
information, contact:
Carla Battle
International Test Conference
Washington, DC, USA
Tel: +1-202-973-8665
FAX: +1-202-331-0111
E-mail:itc@courtesyassoc.com
ITC'99 Program Committee contacts:
PROGRAM CHAIR:
Tony Ambler
e-mail: ambler@mail.utexas.edu
ASIAN CONTACT:
Tetsuo Tada, JAPAN
e-mail: tada@isi.melco.co.jp
Tel: +81-727-84-7448. FAX: +81-727-80-2598
EUROPEAN CONTACT:
Christian Landrault, FRANCE
e-mail: landrault@lirmm.fr
Tel: +33-467-41-85-24. FAX: +33-467-41-85-00
LATIN AMERICAN CONTACT:
Fabian Vargas, BRAZIL
e-mail: vargas@eel.upc.es
Tel: +51-339-1511 x3449
MTDT98 reports a successful workshop with increased attendance
The 1998 IEEE International Workshop on Memory Technology, Design and Testing (MTDT) was held August 24-25, 1998 in San Jose; California, USA. The workshop, sponsored by TTTC and VLSI TC, is the premier event covering all aspects of memory design, process technologies and testability-related issues.
Fabrizio Lombardi, Northeastern University, was the General Chair of MTDT98 while the Technical Program Co-Chairs were Tom Wik, LSI Logic, and David Lepejian, Heuristic Physics Laboratories.
W.R. Bottoms, Chairman and CEO of Credence Systems Corp., kept the audience attentive with his Keynote Presentation that provided insight into current and future trends for the memory industry. In a departure from previous workshops in the series, MTDT98 added two tutorial presentations: SRAM Characterization and Test by S. Murray, Medtronic Micro-Rel, and DRAM Fault Modeling and Test Pattern Design, by B. Cockburn, University of Alberta. The technical program included 19 refereed papers divided into six sessions spanning such areas of interest as embedded-memory design aids, testing techniques, CAM testing, fault modeling and repair. Interested readers can purchase the Proceedings of MTDT98 from IEEE Computer Society Press.
MTDT98 attracted 85 attendees, a significant increase over last year. Also, there was an increase in participation from industry, both local and international. Industry attendance accounted for almost 70% of the total.
In 1999, MTDT will be held again in San Jose. Persons interested in more information about MTDT99, including the Call-for-Papers, should contact Bruce Cockburn, cockburn@ee.ualberta.ca.
F. Lombardi, Northeastern University
STIL (P1450): A paradigm shift in test data standards
For the past two years, the TTTC Standards Committee has supported a Working Group under P1450, which has the longer title "Standard Test Interface Language (STIL) for Digital Test Vectors". And before we go any farther, I need to tell you that the Working Group pronounces the acronym STIL as "style", so if you're talking to a Working Group member please be prepared to talk about "style."
STIL has been in the IEEE balloting process for awhile now. We have completed one re-circulation after the first negative-ballot resolution meeting, and are in the second re-circulation effort in response to comments received from the first re-circulation. This last re-circulation closed on September 28, 1998. Each re-circulation is getting smaller, so we hope to bring this process to a close soon.
That is not to say that the Working Group feels we are finished with this effort. The P1450 PAR (Project Authorization Request) outlined a very specific scope to this effort. STIL must address the "transfer of large volumes of digital test information from Computer-Aided Engineering environments to Automated Test Equipment environments." It requires the inclusion of pattern, format, and timing information sufficient to identify how the test information must be applied to a Device Under Test.
The Working Group feels that the PAR requirements are just the start of this effort. With the support of many companies, evidenced by their continued attendance in meetings, the STIL effort is expanding beyond the current scope, but still contained within digital testing. Notably these new areas are not identified with the "large-volumes-of-data" transportation problem of the current effort. But the drivers for each area have established a new goal of establishing a common syntactic representation for test data.
STIL represents a paradigm shift in the test program environment. With active participation of the original "triumvirate" of IC ATE companies, IC manufacturers, and CAD suppliers, the synergy necessary to define and support a common test data strategy from test 'creation' through test 'application' is present in the Working Group. This synergy caused initiation of the effort even before IEEE support and it continues to drive the group today.
The STIL group held an open meeting at ITC'98 and presented a summary of the STIL effort to date and how various companies are supporting the effort. More information is available on the P1450 website at
http://stdsbbs.ieee.org/groups/1450/
Greg Maston, P1450 Co-chair
P1500 Standard WG seeks task force volunteers to investigate merged cores test requirements
The IEEE P1500 Working Group focuses on facilitating test reuse for embedded cores. At the Working Group meeting on October 18-19, 1998, during ITC'98, a presentation, Lucent's Perspective on SOC Testing, raised an issue concerning test requirements for "merged" cores. The presenter emphasized the growing importance of soft and firm cores, which are typically merged with their surrounding logic. The presenter felt that these cores present test problems similar to those of "non-merged" cores. Merging soft cores and firm cores may not be always desirable from the test perspective and may call for a standard test interface as in the case of "non-merged" cores.
The Working Group agreed to investigate the issue and formed a new Task Force entitled "Mergable Core Test Requirements" to address it. The primary objective of the Task Force is to investigate and identify the test requirements of merged cores (soft and firm) and to verify whether the solutions currently under investigation by the P1500 WG can also address these requirements.
Members from system oriented companies are invited to join this Task Force to help specify the standardization requirements. If you are interested in joining the Task Force, please send email to Sudipta Bhawmik,
bhawmik@lucent.com
For more information on IEEE P1500 check:
http://grouper.ieee.org/groups/1500
or contact Working Group Chair Yervant Zorian zorian@lvision.com
DESIGN & TEST MAGAZINE SPECIAL ISSUES
Special Issue on Microelectromechanical Systems (MEMS)
IEEE Design and Test of Computers seeks original manuscripts for a theme issue on the design and test of Microelectromechanical Systems (MEMS) scheduled to appear in December, 1999. Articles concerning applied research and practical experience reports are solicited. The topics of interest include, but are not limited to:
ü Design and simulation tools
ü Synthesis tools
ü Fault models and failure mechanisms
ü Test methodology development
ü Test generation and fault simulation tools
ü MEMS design and/or test case studies
Authors should submit their original work to the guest editor by January 15, 1999, formatted according to the instructions below. Notification of acceptance will be sent May 15, 1999. Camera-ready copy for accepted papers will be due July 15, 1999. Submitted articles must not have been previously published or currently submitted for publication elsewhere.
Shawn Blanton, Guest Editor
Dept. of Electrical and Computer Engineering
2109 Hamerschlag Hall
Carnegie Mellon University
5000 Forbes Avenue
Pittsburgh, PA 15213-3890, USA
Tel: +1 412-268-2987. Fax: +1 412-268-1374.
E-mail: blanton@ece.cmu.edu
Please address all other correspondence regarding this special issue to:
Submission requirements:
Send six (6) copies of the manuscript in English. Manuscripts are not to exceed 35 double-spaced pages, inclusive of figures and tables, in A4 or 8.5 by 11 inches. Type size must be at least 12 point. Each copy of the manuscript must contain a cover page with author contact information (name, postal address, telephone number, and e-mail address) and a 100-word abstract. Manuscripts must be cleared for publication. Accepted manuscripts will be edited for technical content, structure, style, clarity, and grammar. Detailed information for authors can be found at the Computer Society D&T website at:
http://www.computer.org/pubs/dt/d&t.htm
Special Issue: Test and the Product Lifecycle
A special issue of IEEE Design and Test of Computers magazine will be published coincident with International Test Conference 1999 with a theme based on the conference theme. The theme chosen for the special issue as well as for ITC'99 concerns the impact of test on the entire life-cycle of an electronics product. The Guest Editors seek articles that examine not just chip-level, but also board, system and field-service levels. Most electronic test articles restrict their focus to the product realization level at which the test method is initially applied, e.g. scan path for device test, boundary scan for board test, etc. In many cases, benefits of these test methods can be found at other levels of integration, i.e. chip-level scan test at board design debug via "scan through TAP" modes; field upgrades to CPLD and Flash using in-system programming through boundary scan, etc. The intention of this special issue is to present the TOTAL perspective of design and test throughout the life-cycle of the product
Specifically, we seek articles on the following subjects:
ü Technical and economic views of design and test requirements throughout
a product's life-cycle.
ü The impact on life-cycle costs of re-usable embedded or external test structures.
ü Device and board design methods that enable re-usability.
ü The purpose and nature of re-usability.
ü Aspects of end-user requirements that affect life-cycle availability, reliability and test.
ü Planning and management of a product life-cycle test strategy.
We solicit practical case studies, survey and other technical articles on the above topics and associated topics. The articles will be reviewed to D&T magazine standards.
Submitted articles must not have been previously published or currently submitted for publication elsewhere. Manuscripts must not exceed 35 double-spaced pages of 12-point type, including all figures and tables. Submit six copies of the manuscript by Feb. 1st 1999 to:
Tony Ambler
Department of Electrical and Computer Engineering
The University of Texas at Austin
Engineering Science Building 513
Austin, TX 78712-1084, USA
Tel: +1-512-475-6153
Fax: +1-512-471-5532
E-mail: ambler@ece.utexas.edu
Guest Editors are: Tony Ambler and Ben Bennetts, Bennetts Associates, UK. benb@burridge.demon.co.uk
Changing Positions/Addresses/E-mail
Krishnendu Chakrabarty has moved to Duke University. His new coordinates are: Assistant Professor, Electrical and Computer Engineering, Duke University, Box 90291, 130 Hudson Hall, Durham, NC 27708. Tel: (919) 660-5244. Fax: (919) 660-5293. E-mail: krish@ee.duke.edu WWW: http://www.ee.duke.edu/~krish
After 16 years, Grady Giles has left Motorola and is pursuing a venture involving embedded DRAM. He can be reached at 16200 Goldenwood Way, Austin, TX 78737. Tel: 512-858-4878. E-mail: gsquared@gte.net
Carol Q. Tong, has accepted a position at Cisco. Her new coordinates are: Cisco Systems, Inc., 170 West Tasman Dr., SJ-N2, San Jose, CA 95134-1706. Tel:(408)525-1223. Fax: (408)527-2324. E-mail: cqtong@cisco.com WWW: http://www.cisco.com
Jon Udell has new coordinates: 4304 Whippeny Drive, Fort Collins, CO 80526. Tel: (970) 225-0869. E-mail: Jon.Udell@pobox.com
Keep in touch! Let your colleagues know where you can be reached. If your position, address, e-mail, etc. are changing, please let us know. E-mail your change to tttc@computer.org
To Apply for TTTC Membership or Change your Mailing or E-mail Address,
Send e-mail, postal mail, or call:
Test Technology TC Office, 1474 Freeman Drive, Amissville, VA 20106
Tel: (540) 937-8280. Fax: (540) 937-3739. E-mail: mhcem@aol.com
Include the following information:
« What you want to do -- join TTTC, renew membership, change postal or e-mail address, etc.
« IEEE or Computer Society member number, if you are a member.
« Complete address including: first name, family name, affiliation, internal mail address (dept., mail stop, etc.), postal address, City, State/province, postal code, country.
« Telephone number and E-mail address
Membership in TTTC is open to everyone interested in test engineering at a professional level. TTTC has NO dues or parent-organization membership requirements. However, registration fees for TTTC-sponsored meetings & tutorials are substantially reduced for members of IEEE or IEEE Computer Society, which do have member fees.
This newsletter is the informal publication of the IEEE Computer Society Test Technology Technical Council. We will publish all appropriate material although editing may be necessary to meet space or typographical constraints. Articles are not refereed unless so noted. Opinions are those of the contributors and are not necessarily the opinions or positions of TTTC, the IEEE, or the IEEE Computer Society.
Contributors who wish to have their employers name included with their byline must specifically request it with their contribution. Contributors bear responsibility for any issues that may arise with their employer as a result of their contribution.
TTTC
Chair: Yervant Zorian
Editor: Ed Thomas
Publisher: Maddie Harwood
Associate Editors Mike Keller, Don Lenhert (D&T Magazine),
Ian Dear (Europe), Teruhiko Yamada (Asia)
SEND CONTRIBUTIONS TO: TTTC Office, 1474 Freeman Drive, Amissville, VA 20106. Tel: +1 540 937-8280 E-mail: tttc@computer.org
PREFERRED SUBMISSION FORMAT: electronic mail in ASCII text format or Rich Text Format
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