24-26 October 2001, San Francisco, CA, USA

DFT is an annual Symposium providing an open forum, combining new academic research to state-of-the-art industrial data, for discussions on all aspects of design, manufacturing, test, reliability and availability that are affected by defects during manufacturing and by faults during system operation. Topics include defect and fault tolerance issues, error detection and recovery, yield and dependability analysis and modeling, testing techniques, yield enhancement techniques, applications and case studies.

• 16 tutorials covering such diverse topics as boundary-scan, mixed-signal DFT, DFT for system-on-a-chip, test challenges for low-voltage CMOS. A generous supply of knowledge for the test professional to keep up with new technologies.
• Special panels on the economics of SOC testing, and another contrasting the historical issues involving structured test with those of today.
• The formal opening of the conference begins with the plenary session keynote address by Sue Billat, managing director of Robertson Stephens, discussing Wall Street's Perspective on Test Trade-offs. Phil Nigh, of IBM Microelectronics, will then give an invited talk on the challenges of using "cheap DFT testers", while at the same time improving product quality.
• The technical program expands on the conference theme with sessions on BIST, SOC testing, embedded core testing, RF testing, diagnostics and many more state-of-the-art topics. Papers on research topics as well as new developments in the test industry will be presented.
• Technical program supplemented with lecture series on board test, logic BIST case studies, and embedded DRAM testing and repair.
• Concurrent with the technical program, ITC includes an exhibit floor products from the major suppliers in the test industry. See the newest equipment, software, services, and tools from all over the world for solving your test problems. We are continuing to reduce the overlap of technical program and exhibits to accommodate those who wanted to attend both activities, but could never find the time.
• More thought-provoking panels to explore current issues challenging the test practitioner. This year's topics include the dichotomy between low-cost and high-power ATE, the challenges of managing test, ac scan, along with many others that help the test professional expand his or her horizons.
• To close Test Week, ITC hosts three workshops, Resource Partitioning (TRP) Yield Optimization Test workshop (YOT), and the new Workshop on Test of Wireless Circuits and Systems (WTW).

General information: ITC Office +1 202-973-8665; email: itc@courtesyassoc.com. Exhibitor Information: Jill Sibert +1 610-758-8190 email: j.sibert@advantest.com

19-21 November 2001

The Asian Test Symposium (ATS) provides an international forum for researchers and engineers from all over the world especially from Asia, to present and share state-of-the-art ideas, technologies and designs for electric devices, assemblies and systems. The program committee has put together an outstanding technical program of both regular and poster sessions. The poster sessions are devoted to introducing DFT application to real chips from industries and practical ideas from universities. The keynote address will be given by Dr. Janusz Rajski, Chief Scientist, Mentor Graphics Corporation, entitled "DFT for High Quality, Low Cost Manufacturing Test." Besides the paper sessions, two half-day tutorials are offered: "Testing Memories and Embedded Memory Cores: Fault Models, Algorithms, DFT, BIST, BISR and Industrial Results" by Prof. A. J. van de Goor; and "Testing Embedded-Core-Based System Chips" by Dr. Erik Jan Marinissen and Dr. Yervant Zorian. To celebrate this 10^th ATS, "The Tenth Anniversary Compendium of Papers from Asian Test Symposium" will be published by the sponsors NEC, Hitachi and Fujitsu. Furthermore, to commemorate significant contributions of late Professor Teruhiko Yamada to Asian Test Symposiums since 1992, the Teruhiko Yamada Memorial Fund has been established and Teruhiko Yamada Memorial Awards will be presented to students with high quality papers and others who have contributed to the development of Asian Test Symposiums.

22-23 November 2001, Nara, Japan