Test Technology Newsletter

January -February, 1997

The Newsletter of the Test Technology Technical Committee of the IEEE Computer Society

All TTTC members are welcome to attend TTTC's Operations Committee meetings. The next meeting will be held during VLSI Test Symposium, Hyatt Regency Monterey Hotel in Monterey, California USA, April 28-30, 1997. All TTTC group chairs, meeting chairs and TAC chairs should prepare written reports for the meeting. Watch for a meeting schedule and agenda.

Zorian proposes expansion of TTTC activities in 1997

With this first issue of the Newsletter in 1997, I would like to welcome you to a new year of TTTC activities, during which I hope you will be able to contribute and to enjoy participating in our wide range of activities, such as workshops, Technical Activity Committees, tutorials, standards, etc. Following the success of 1996, still another record year seems to be ahead of us. We are planning to expand our activities in three ways: by widening the spectrum of topics we are involved in; by expanding our base of recipients; and by improving communications both to you and from you.

I would like to share some of our plans with you.

1. To broaden topical areas, we are encouraging the creation of (1) several new TACs; (2) new workshops, e.g. one on embedded core testing, another on yield improvement and a third on signal propagation on interconnects; (3) new tutorials; (4) roundtable discussions on key emerging topics published in Design and Test magazine; and (5) technical exchanges featured in our newsletter on hot controversial topics, such as the recent articles on MOS scaling effects on IDDQ testing and the article on asynchronous testing.

2. To deliver our products to more people in our community-at-large, we plan to publish some of the papers from our conferences and symposia in other publications such as special issues of archival journals in addition to their corresponding proceedings. For example: VTS '96 will be featured in IEEE Transactions on CAD; the special diagnosis and failure track of ITC '96 will be in IEEE Design and Test; On-Line Test Workshop '96 in JETTA; and VTS '97 will be in IEEE Transactions on VLSI. We also are extending the coverage of our educational program by offering more tutorials: we have already increased from two to five the number of tutorials at VTS '97. Finally, we are planning to increase our membership base by more explicitly inviting our technical meeting attendees to join TTTC.

3. In terms of increasing the flow of information with you, we plan to reach you more frequently via our newsletter. We have increased the publication frequency to six per year for this newsletter, while maintaining the four issues that are embedded in D&T magazine. We encourage you to communicate with us about TTTC, about test issues, or about test people. Please do not hesitate to use the TTTC Office or my personal contact coordinates to reach us. We welcome your suggestions, your feedback, and, most of all, your contributions to our publications, meetings and activities. I also want to thank Fred Liguori, TTTC Chair for 1995 and 1996, and his team for their excellent efforts, the fruitful results of which will be the basis for our work this year. And I want to welcome the newly assigned TTTC operating team for 1997. (See Volunteer Leaders, below.)

Last but not least, I would like to extend my thanks to TTTC members for the trust you expressed in me by electing me to serve as your 1997 Chair. Let us all work together to nurture our test community and contribute to our own professional development and that of our fellow TTTC members.

Yervant Zorian, zorian@lvision.com

TTTC has sponsored tutorials at VLSI Test Symposium for a number of years. These tutorials are designed for professionals who wish to learn a new topic, to learn about recent advances in a topic or to get a refresher in the subject. Because of the success of past tutorials and the growth in the test community, we are expanding our tutorial program at VTS for 1997. We are offering two new, leading edge topics on Sunday, April 27, before the symposium as well as three tutorials on Thursday May 1, after the symposium.

On Sunday, April 27th, the two tutorials are:

New Validation and Test Problems for High Performance Deep Sub-micron VLSI Circuits, M. Breuer -USC, C. Gleason -HP, S. Gupta -USC. This tutorial focuses on the emergence of new validation and test issues, factors motivating the emergence of these problems, basic models and the analysis of the underlying electrical phenomena, and several case studies.

Systems-on-a-Chip: Design and Test Practices, S. Dey -NEC USA, Y. Zorian -LogicVision. This tutorial addresses the challenges and current industrial practices in the design, validation and test of systems-on-a-chip, which many believe will dominate system design methodology by the year 2000.

On Thursday, May 1st, the three tutorials are:

Error, Fault, and Defect Diagnosis: A Detective Story, M. Abramovici -Lucent Technologies Bell Labs, R. Aitken -Hewlett-Packard. The focus of this tutorial is on advanced diagnosis topics: methods for locating defects such as opens, shorts, and leakage in transistor-level circuits; approximation techniques for identifying unmodelled faults with a dictionary; AI techniques; IDDQ-based diagnosis; diagnosis for delay-faults; BIST and diagnosis; design-for-diagnosability techniques. Basic diagnosis concepts are also briefly reviewed.

Mixed-Signal DFT & BIST: Practices and Realities, A. Chatterjee -Georgia Institute of Technology, B. Kaminska -Ecole Polytechnique de Montreal, S. Sunter -LogicVision. Three important questions will be answered -What structured DFT methods are in use today? How can the effectiveness of analog tests be measured? How should DFT and BIST methods be evaluated? Topics discussed include: mixed-signal defects and faults, test metrics, fault simulation, automating test generation, design-for-test methods, and the emergence of built-in self test for mixed-signal circuits.

Test Solutions for Deep Submicron Memories, D. Lepejian -HPL. This tutorial introduces today's deep-submicron memories and their variations and associated challenges. Included are discussions on embedded SRAMs, DRAMs, flash memory, ROM, CAMs and Multiports. We will discuss test strategy development starting from fault modeling and fault-model generation, development of reduced-complexity test algorithms and special testability modes for DFT Also included are built-in self-test and built-in self-repair needs and approaches, memory fault diagnosis, and an introduction to alternatives to physical failure analysis.

Mark your calendars! More detailed descriptions of the tutorials and registration information will be included in the VTS Advance Program.

J. Monzel, TTTC Tutorials Group Chair

J. Figueras, VLSI Test Symposium Tutorials Chair

Changing Positions/Addresses

Pat McHugh, has accepted a new position at LogicVision, Inc. His new coordinates are: LogicVision, 602 Sixth Avenue, Asbury Park, NJ 07712 USA. Tel: (908) 869-1812, Fax: (908) 869-1955, E-mail: pmchugh@bellatlantic.com, Pager: (800) 946-4646 enter PIN 547-3467.

Tom Williams is temporarily on leave from IBM and is working in Germany. He is at Universitaet Hannover, Institut fur Theor. Elektrotech., Appelstr. 9A, D-30167 Hannover, GERMANY. Tel: +49 522 762 5031, Fax: +49 511 762 5052, E-mail: twilliam@tet.uni.hannover.der

Are your coordinates changing! Update 1000+ test professionals by sending us your new coordinates.

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Fifth Asian Test Symposium (ATS'96) Attracts World-wide Attention

One hundred and eighty-four participants from around the world gathered in Hsinchu, Taiwan, November 20-22, 1996, for the Fifth Asian Test Symposium. This year we received 85 papers. Twenty papers were from Taiwan, as local researchers and practitioners responded to our promotion of the Symposium with enthusiasm. Fifteen came from Japan, 14 from the US and Canada, 10 from China, five from Korea, three each from France, Germany, Russia, and the Netherlands, and nine from the rest of the world, including Belarus, Belgium, Brazil, Egypt, Hong Kong, Pakistan, Poland, Singapore, and Switzerland. From these submissions, 46 papers were presented in 10 sessions that covered most of the current topics on test & design techniques.

On November 20, we had four tutorials; Basic Memory Testing and Advanced Memory Testing by Prof. Ad J. van de Goor, and Mixed-Signal Fault Models and Design for Test I and II by Prof. Mani Soma and Prof. Chin-Long Wey. The tutorials were very successful, attracting a total of 91 attendees.

On November 21, Prof. Sudhakar M. Reddy addressed the critical issues that test researchers face and their possible solutions in a keynote speech entitled Challenges in Testing. That evening, a panel discussion, Testing of Low Power Circuits and Systems: Are There Any Need for Special Considerations? was held. At the end of the one-and-a-half-hour discussion, most agreed that the low power requirement should be viewed as just another important requirement which designers must face. While there may be conflicts among low power, high testability, high performance, low cost, etc., designers, as usual, will give weights to all of these parameters in the optimization process.

On the morning of November 22, Prof. Kwang-Ting Cheng gave a keynote address entitled Built-In Self-Test for Analog and Mixed Signal Designs: the Opportunities and the Challenges. The importance and the difficulties of analog and mixed-signal IC testing were discussed and DSP-based analog BIST was presented. That afternoon we had the technical tour to the Science-Based Industrial Park. Thirty-eight people visited the Chip Implementation Center of the National Science Council, the Science-Based Industrial Park Administration, and the Nano Device National Lab.

In 1997, ATS will be held in Akita, Japan, November 17-19, 1997. The date of submission is April 15, 1997. More information is available from http://ats97.cs.ehime-u.ac.jp/

Cheng-Wen Wu, ATS'96 Technical Program Chair

The IEEE 1149.4 Mixed-Signal Test Bus working group is forming a ballot group to review their draft standard which is expected to go to ballot in June 1997. The standard is intended to provide an "interface system" between mixed-signal components, modules, or systems and external or built-in test equipment. It is aimed at providing those components, modules, or systems with standardized testability attributes. The standard will define and describe the signals, functions and characteristics of the test bus and how it is to be implemented. Application of the standard will improve controllability and observability of mixed-signal designs and test quality while reducing test-development time and cost. For an invitation to ballot please contact Terry Lee at (908) 562-6532, or send email to: t.t.lee@ieee.org.

1149.1 (JTAG) due for revision

The IEEE 1149.1 (JTAG) standard is up for revision. Anyone interested in joining the balloting group for this standard should contact Carol Buonfiglio at (908) 562-3834 or email to c.buonfiglio@ieee.org. People involved in either implementing (manufacturers) or using the 1149.1 standard are needed to ensure that the balloting group is balanced.

P. McHugh, Standards Group Chair

The 15th Annual VLSI Test Symposium will be held at the Hyatt Regency Monterey Hotel in Monterey, California from April 27 to May 1, 1997. VTS '97 will explore state-of-the-art concepts and trends in testing of electronic circuits and systems. This year's theme is: Innovations in Test and Diagnosis: from Embedded Cores to Systems.

The symposium is designed to provide an informal and vibrant forum for discussing and exchanging innovative ideas in testing. VTS '97 will feature a high-quality program of twenty paper sessions that will discuss issues in: verification and debugging, analog circuit testability, core and processor test, memory test, IDDQ test, thermal testing, BIST, etc.

In addition to formal paper sessions, the organizers have arranged for a number of very interesting tutorials and panel sessions. The tutorials are described in the article starting on page 1. Panel topics include:

- Microprocessor Test and Validation: Any New Avenues?

- Will 0.1m Digital Circuits Require Mixed-Signal Testing?

- ATE for VLSI: What Challenges Lie Ahead?

- Thermal Testing: Why Do We Need It?

- System on Silicon: Design and Test Challenges

- Power Dissipation during Testing: Are There any Concerns?

VTS '97 will feature a special session on Sematech's recent experiment on the relative effectiveness of different test methods. In addition, Dataquest's Gary Smith will present an invited address, Challenges in Emerging Technologies.

If you are serious about testing and looking for ways to help improve it, you should not miss the VTS '97. Register by April 1 to receive lower registration rates and to ensure a place for an exceptional Social Program: Exploring Beautiful Monterey.

For more information visit our WWW site at:

http://www.computer.org/tab/tttc/meetings/vts/home.html

To get the VTS '97 Advance Program, fax your complete address to the TTTC Office, fax: (814) 941-4668, call us at: (814) 941-4669, or send e-mail to: EdDor@aol.com

B. Kaminska, VTS Publicity Chair

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Mixed-Signal Test TA undertakes

analog circuit benchmark development

For a long time researchers and practitioners working in analog and mixed-signal testing have complained that they were unable to compare results as it is done in the digital domain. In particular, fault modeling and test generation have been a significant concern. Now, however the Mixed-Signal TAC has obtained permission from Mitel Semiconductor to use their 1.5um CMOS technology to develop benchmarks for the analog domain. The first group of volunteers from industry and academia have signed up for some typical circuit development and/or revision. At least two revisions are planned for each circuit.

In the near future, three meetings are planned that will discuss this work and related matters: first, in Europe, at European Design and Test Conference, March 17, 1997, the second, in Monterey, CA at IEEE VLSI Test Symposium, April 28-30, 1997, and the 3rd, in Seattle, WA, at the 3rd International Mixed-Signal Test Workshop, June 3-6, 1997. A first set of benchmarks should be announced at the latter meeting. For details about the meetings, refer to the corresponding meeting programs.

Volunteers willing to help or to be informed will be very welcome. For more information, please contact: Bozena Kaminska, e-mail: bozena@vlsi.polymtl.ca

B. Kaminska, Mixed-Signal Testing TA Chair

Because its application to products has had such a high pay off, "Accelerated Reliability Testing" has become one of the latest buzz phrase in the testing industry. The HALT and HASS techniques were initially developed by Dr. G.K. Hobbs of the Hobbs Engineering Corporation using well-known Electronic Stress Screening techniques in a new and unique way. ESS has been used for several-dozen years to check the reliability of a design.

HALT is the acronym for Highly Accelerated Life Test and HASS stands for Highly Accelerated Stress Screen. The two stresses used by the HALT/HASS techniques are rapid temperature transitions and random vibrations. Here is a quick, simplified outline how the HALT/HASS process works.

HALT is used during the design stage of any electrical and/or electro-mechanical product that has already been bread-boarded. It basically subjects the design to a combination of ever-increasing stresses, monitoring the design outputs to their failure stage (far above design specifications). Fixes are then made to the design and the process is repeated until a design is obtained with a very well understood specification of destruct limits. This HALT process helps a manufacturer to ruggedize a specific design.

HASS is used after the product has been designed and is about to enter manufacturing. Here the product is tested just above the upper and lower limits of its specification (typically +/-20% of the operational limits), but not to the destruct limits found earlier by HALT The testing is carried out in such a manner that it finds defects in the building process without removing significant life from the product. Often "seeded samples" with known defects are sent through the HASS process to help adjust the levels of the HASS profile and determine at what level it identifies a specific type of failure. After these HASS profile adjustments are made, previously unstressed samples are run through the profile as many as 50 times to determine the effectiveness of the profile and to complete what is called the proof-of-screen process.

During serial production, a variation of the HASS process ensures that the product reliability gains achieved through HALT/HASS are maintained throughout the production process.

HALT/HASS has been used by dozens of companies who have experienced substantial cost savings and increased product quality. Proprietary test systems that support HALT/HASS are commercially available and there are a number of independent test laboratories that specialize in performing HALT/HASS for customer products. For more information, contact Michael Keller, e-mail: mkeller@VAX3.drc.com

M.E. Keller, Associate Editor

1997 European Design & Test Conference

Measured by the number of submissions, ED&TC 97 is the largest event of its type in Europe! ED&TC received about 300 regular submissions, from which an international review panel has selected 93 papers for inclusion in the IEEE Proceedings and 24 User's Forum papers.

This year, there are three major new trends at ED&TC:

1. About one-third of the papers are concerned with innovative system-design techniques. Papers from industry such as those from Philips, Siemens, Canon, IBM, et. al. tend to illustrate working design methodologies where executable specs in C or C++ are systematically refined into synthesizable VHDL modules. These methodologies have been applied in areas ranging from video to multimedia and networking components. On the other hand, academic research is dominated by new techniques and computational models for software synthesis in embedded systems with real-time constraints. Examples such as MPEG, video and digital communications, illustrate their methods. Also remarkable is that a number of industries and academic institutions present new solutions to the synthesis and optimization of memory architectures which tend to dominate data-intensive applications such as video and multimedia. Certainly new is the fact that system-level CAD no longer focuses on toy examples but now attacks state-of-the-art design problems.

2. The number of papers on mixed-analog/digital systems has gone up significantly. Mixed signal is a particular strength of the European community. Especially novel methods for on-chip testing of data converters will be presented, as well as synthesis methods for sigma-delta converters and analog-sensor interfaces, automated place-and-route for analog systems and advances in symbolic analysis of large analog circuits.

3. ED&TC offers three sessions devoted to new methods for power modeling and estimation as well as synthesis techniques for low power.

Of special interest to TTTC members are 11 sessions on the latest advances in test technology research. Some notable trends are: the moving of testability concepts to register-transfer and behavioral level; new, low-overhead DFT techniques to enhance testability; novel methods to estimate testability of behavioral specs; self-checking data-path operators with less than 20% overhead; advances in BIST where optimal LFSR and cellular automata are synthesized to generate tests for delay; and CMOS stuck-open faults. Of course, there will be a number of papers on IDDQ testing, including on-chip current monitors and on methods to keep IDDQ going even for deep-submicron technology.

Layout issues are dominated by deep-submicron interconnect modeling and analysis. Researchers from IBM, Lucent and Philips will present exciting new information on the importance of inductive-effect modeling for low-voltage circuits, on optimizing interconnect shapes and on modeling 3-D capacitive effects. In the area of logic synthesis, a unified framework for graph optimization in CAD applications based on ZBDD's and a novel, efficient synthesis technique for gated clock architectures will be presented

Other presentations will focus on formal verification methods that build on BDD's and Signal Flow Graph tracing. The latter is also successfully applied to a mixed analog/digital-interface design example.

Three keynote speakers will introduce the technical program. J. Meindl, Georgia Institute of Technology, will speak about the limits to growth in silicon technology. A. De Geus, President and CEO of Synopsys, will speak about systems-on-a-chip, and B. Pehrson, of KTH in Stockholm, will present the evolution of telecom and multimedia. A European dimension will be brought to the keynote session by Session Chair G. Metakides, Director of IT Programme at the European Commission.

ED&TC again will feature the successful hot-topic sessions inaugurated last year. This year, the hot topics include networked CAD systems, deep-submicron CAD and multichip packages for consumer applications. Also, an embedded tutorial, Hardware-Software Co-Design in Europe and USA: A Collaborative Initiative will be given by D. Gajski, University of Irvine, and R. Ernst, University of Braunschweig.

Once again, ED&TC will offer a User Forum which will report the latest industrial and academic experience in circuit design. Together with a poster session, the User Forum will allow for direct interaction with authors. Three panels will discuss the following questions: "How to Introduce Advanced Design Technology in Qualified Industrial Design Flows?," "What will be the Right Test Methodology for the Year 2005?," and "Are There Conflicts of Interest in IP Based Business?" Tutorials will also be available on hot issues in design and test of ASICs and Systems.

Concurrent with the Conference is a full-scale, international exhibition, featuring the world's leading suppliers of design and test products. The exhibition will feature a theatre running technical presentations from exhibiting companies, which will be free of charge to all visitors to the exhibition.

A last touch is a gala dinner and at the top of the famous Centre Georges Pompidou, with the opportunity to view the Paris National Museum of Modern Art.

ED&TC 97 is sponsored by EDAA, the IEEE Computer Society DATC and TTTC, and ACM/SIGDA, in cooperation with other European Societies. Visit ED&TC on the WEB: http://www.imec.be/edtc/97/

B. Courtois, ED&TC Publicity Chair. E-mail: bernard.courtois@imag.fr

new applications in technical education

The concept of MENTORING has been around for centuries, but the need is now becoming apparent in technical education. TTTC member Art Bainton is working with Quinsigamond Community College, a two-year technical college in the Worcester, Massachusetts area, to define a mentoring program. Preliminary work has identified that the area of greatest need is "English-as-a-Second-Language" students working toward a technical degree who need assistance entering the job market. Initial efforts will focus on working one-on-one with these students.

Mentoring may be likened to a "big-brother" strategy where the mentor spends time with the student to get to know his or her interests and strengths, and, more importantly, to learn how to effectively communicate with each other. Communication is the real challenge. Clearly the mentor will initially assist the student in understanding technical journals and other technical media, so a natural meeting place for mentor and student is a good technical library, such as at a major university. In Bainton's case, Worcester Polytechnical Institute serves that function well.

Together the student and mentor work to identify the student's existing strengths and career interests. The student is expected to study in areas of his or her special interest on an independent basis in order to develop a level of expertise and technical currency. This enables the student to speak knowledgably and fluently in a specific area. Developing a foundation of self-taught knowledge is of key importance because it is a genuine quality that comes across in an employment interview. The more adept the student becomes in the self-learned area, the more obvious it is to a potential employer that the student can harness skills to meet the employer's immediate needs.

There is another benefit to the self-taught expertise. The student's fluency in speaking about his area in English convinces the potential employer that there will be a tolerable learning curve in picking up the verbal and written language requirements for the job.

Clearly mentoring requires time and diligence. The mentor's knowledge and expertise must match the student's interests and career path. In addition the mentor must be a giving type of person.

The Quinsigamond pilot program requires at least two mentors and three students. While the college definitely can provide the students, mentors are still being sought.

The Quinsigamond mentoring pilot program is just a beginning: the concept should be useful in other similar areas throughout the country. Perhaps TTTC's Educational TA could sponsor a small network of mentors who could help each other and share experiences, techniques and training aids.

Those interested in mentoring, please contact Art Bainton, abbainton@mcimail.com

A. Bainton

Southwest Test Workshop

San Diego, CA, USA

May 31 -June 3, 1997

The 1997 Southwest Test Workshop will be held from Sunday evening May 31 through Wednesday, June 3 in San Diego, California. For the fourth year, the workshop will focus on microelectronic wafer-probe testing. This workshop is the only IEEE-sponsored technical forum for this specialized area of testing.

Activities begin with registration, a reception, and a panel discussion Sunday evening. A videotape of the panel session will be given to the audience at the conclusion of the workshop.

Technical presentations will begin Monday morning. During two-and-a-half days, eight sessions of three to four viewfoil presentations each will cover a wide variety of probe related issues, such as RF probing; material research; probe-card metrology; membrane probe cards; advanced probe-card technology (fine pitch & high pin count); improving efficiency in wafer-sort operation; vertical probes (Cobra/buckling beam); and probe potpourri.

The presentations will provide a balanced forum with wafer manufacturers' current best practices and vendors' ready-to-buy solutions for current problems.

For registration or more information contact Bill Mann at (714) 221-3132, E-mail: william.mann@nb.rockwell.com.

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Rapid Systems Prototyping Workshop

The Carolina Inn-Chapel Hill, North Carolina

June 24-26, 1997

The IEEE International Workshop on Rapid System Prototyping presents and explores the trends in rapid prototyping of computer-based systems including, but not limited to, communications, information, manufacturing and transportation systems. The eighth annual workshop will focus on improved approaches to resolving prototyping issues and problems raised by incomplete specifications, increased system complexity and reduced time-to-market requirements for a multitude of products. The workshop will include a keynote presentation and formal paper sessions with a wide range of system prototyping topics, which include, but are not limited to system emulation, virtual prototyping, hardware-software codesign, tools for hardware prototyping, tools for software prototyping, the role of FPGAs in system prototyping, prototyping case studies, very-large-scale-system engineering, hardware/software tradeoffs, system verification/validation and prototype-to-product transition.

For more information, contact Nick Kanopoulos, Tel: (919) 462-6567, Fax (919) 462-0300,

E-mail: nick@dct.rti.org

WWW: http://www-masi.ibp.fr/rsp

Sofitel Capsis Beach Resort, Aghia Pelaghia Headland,

Crete, Greece

July 7-9, 1997

The increased complexity of electronic systems has seen increasing reliability needs in various application domains as well as pressure for low-cost products. There is a corresponding increased demand for cost-effective on-line test techniques. This workshop provides an informal forum to discuss all aspects of on-line testing.

Topics include concurrent checking; periodic testing in the field; field diagnosis; self-checking digital, analog and mixed-signal circuits; coding theory; on-line and off-line BIST; synthesis of on-line testable circuits; radiation hardened/tolerant process and design techniques; Sensors/detectors for on-line monitoring of current, temperature and other reliability relevant parameters; fault-tolerant and fail-safe systems; and on-line testing in automotive, railway, avionics, industrial control and space applications.

For general information, contact Antonis Paschalis,

Tel: +30 1 65 20 847, Fax: +30 1 65 32 175,

E-mail: paschali@iit.nrcps.ariadne-t.gr

Hilton Hotel and Towers, San Jose, CA, USA

August 11-12, 1997

The workshop will include all aspects of memory design, process technologies and testability-related topics. Memory circuits design, cell structures, fabrication processes, design architectures as related to testing, verification and test methods for SRAM, DRAM Flash and Non-volatile memories, EPROM, EEPROM embedded memories, logic-enhanced and FIFO memories, 3-D memories and content addressable memories.

For more information contact Fabrizio Lombardi,

Tel: 409-845-5464, Fax: 409-847-8578,

E-mail: lombardi@cs.tamu.edu.

Call for Participation

Cannes "Cote d'Azur", FRANCE

September 21-23, 1997

THERMINIC Workshops are a series of meetings to discuss the essential thermal questions of microelectronics and microstructures. These questions are becoming more and more critical with the increasing element density of deep-submicron downsizing of integrated circuits necessitating thermal simulation, monitoring and cooling. The high element density of MCMs and mobile parts of microsystems raise new thermal problems that must be solved in the near future. On the other hand, thermal effects can be used as a basis of sensors and other functional structures. Areas of interest are: thermal and temperature sensors; thermal simulation; electro-thermal simulation; thermal modeling and investigation of packages; evaluation of thermal measurements; and temperature mapping.

Authors are invited to submit papers describing recent work. Panel proposals are also invited. Papers may be extended summaries (minimum 500 words) or full papers. In either case, clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. On the title page please indicate: title, name and affiliation of all authors, an abstract of 50 words or less, and suggested topics. Also identify a contact author and include a complete mailing address, phone number, fax number and E-mail address.

Submit 5 copies by April 30, 1997 to Bernard Courtois, TIMA, 46 Avenue Felix Viallet, 38031 Grenoble cedex, France. E-mail: Bernard.Courtois@imag.fr.

D. Lenhert, Newsletter Editor D&T

Doris and Ed Thomas

The IEEE Computer Society Board of Governors recently announced a resolution recognizing and honoring Doris E. Thomas and Edward W. Thomas for their many years of service to International Test Conference in both volunteer and professional capacities. The resolution was announced at the ITC Awards Banquet on October 20, 1996, by Michael Elliot, Computer Society Executive Director, who also presented a copy of the resolution and a plaque to the Thomases.

Following is the text of the resolution:

WHEREAS the International Test Conference has long been one of the most successful conference series sponsored by the IEEE Computer Society;

WHEREAS Doris and Ed Thomas have served the International Test Conference in both volunteer and professional capacities for more than 17 years;

WHEREAS their dedicated service over those 17 years has been characterized by an unusual degree of devotion and achievement;

WHEREAS their capacity and willingness to provide guidance to the conference steering committees and their extensive interactions with other society volunteers and with society staff were vital to promoting the success of the conference;

WHEREAS the success of the International Test Conference is in large measure due to their support and participation in all aspects of the conduct of the conference; and

WHEREAS Doris and Ed Thomas have announced their retirement as conference managers for the International Test Conference;

NOW, THEREFORE, the Board of Governors of the IEEE Computer Society gratefully acknowledges their many years of dedicated service and extends its best wishes to Doris and Ed for a happy and prosperous future.

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Doris started her association with ITC in 1979 as a volunteer on the registration staff. In 1980 and 1981 she served as ITC Secretary/Registrar. In 1982, as the administrative tasks involved in running the rapidly growing conference began to surpass the resources of a volunteer committee, the General Chair at the time asked Doris to provide full-time office services to ITC. In 1985, Doris incorporated TMS, Technical Meeting Services. By this time, TTTC had asked Doris to provide services for the committee, its tutorials and workshop and other activities to take advantage of the synergisms possible because of TTTC's and ITC's common interests and interfaces. By 1994, TMS grew to a staff of five devoted to providing services to ITC and TTTC.

Ed began his association with ITC as a member of the Program Committee in 1977 when the meeting was still known as the Cherry Hill Test Conference. In 1980 he was conference General Chair. Ed maintained his ITC volunteer role until 1989, serving in a number of roles, including Planning Chair and Test Week Coordinator. Ed has also been an active volunteer with TTTC, serving as TTTC Chairman in 1982 and as Newsletter Editor and TTTC Secretary in various years. On retiring from AT&T, Ed joined TMS in 1990. He expanded TMS's operations into publishing and marketing support to meet the needs of TTTC activities for affordable promotional and printed material.

In December 1995, Doris notified ITC that she would retire after the 1996 ITC. During 1996, ITC proceeded to select a new service vendor, Courtesy Associates, of Washington, DC. Doris and Ed have agreed to continue to provide services to TTTC for one or two years until they find a satisfactory replacement. Ed will continue as TTTC Newsletter Editor in 1997.

J. Monzel, TTTC Awards Chair

Biographical material supplied by E. Thomas