Test Technology Newsletter
July -- August, 1997
The Newsletter of the Test Technology Technical Committee of the IEEE Computer Society
CHAIRMAN'S MESSAGE:
Are we fulfilling our responsibilities?
In our daily functions, each one
of us, as a test professional, has individual responsibilities for creating,
developing and implementing test solutions. Such individual efforts directly
correspond to the requirements of our own specific projects or products.
Test technology has always played the role of enabler to ensure
the quality of electronic systems during their manufacturing and usage in the
field. With the recent advancements in the electronics industry, the cost of
testing is rising sharply. For instance, test development cost has risen from
22% of total chip development cost in 1988 to 40% today, according to
Dataquest. In line with this trend, Sematech predicts that chip testers will
reach a cost of $50 million by year 2010; while vertically integrated companies
will see their test cost reaching 40% of total production cost. This
demonstrates simply that the impact of test technology on the overall cost of
electronic products is becoming more and more critical.
If we, as test professionals, invest only in our individual
efforts to meet the requirements of our specific projects, we can only have a
very limited impact. Such action will not allow us to fulfill our
responsibilities toward our projects and the industry at-large. However, if we
tap into collective efforts, our impact can be very different. Global
optimization in such cases is clearly more effective than isolated and local
optimization. For instance, if we participate in collectively specifying
critical testing problems, determining common needs, and analyzing potential
solutions, our understanding of today's test technology challenges will
definitely become broader and hence our contribution to their solutions will be
much more comprehensive, effective and long term.
One unique vehicle that allows for such a collective efforts is
our own TTTC. Its technical activity committees (TACs) are meant to specify the
critical testing problems mentioned above. Seventeen TACs galvanize the key
experts in each new test domain. Recent new TACs include thermal testing,
verification, and defect tolerance. In addition, TTTC's standardization effort
is meant to determine the industry-wide needs for common solutions. A recent
initiative is IEEE P1500, a proposal to standardize the interface between an
embedded core and its host, the system-on-chip. TTTC workshops, symposia and
conferences provide an excellent forum for the analysis of potential solutions
for today's problems and provide a channel for constructive feedback to the
proposed methods.
During the last four months, ten TTTC workshops and symposia took
place: almost all of them achieved record participation. This clearly reveals
that large numbers of test professionals and their organizations acknowledge
the benefits of such collective efforts and see their participation in them as
part of their responsibilities.
Our opportunities to participate in numerous types of collective
efforts are an unparalleled service that TTTC has offered for the last twenty
years. As test technology becomes more and more critical for the electronics
industry, TTTC's services will become even more valuable. In addition to the
above offerings, TTTC will extend its role by creating new collective efforts.
Soon you will hear about the creation of an Industry Advisory Board, expansion
of our tutorial program, new workshops, the revitalization of TTTC's web
offerings, initiation of a TTTC Latin American Group, and the redefinition of
this Newsletter.
Don't be left out. TTTC's collective efforts are beneficial to
you, to your company, to the test community and to the industry at-large. These
projects can only be accomplished through the efforts of dedicated test
professionals like you. In this changing world, being just a TTTC member and a
passive attendee in events is simply not enough to fulfill our role as
professionals. I extend an invitation to each one of you to take an active role
in TTTC and participate in organizing these and other collective efforts. Chose
your domain, come up with suggestions, and send me a note.
Are you fulfilling your responsibilities as a test professional
today?
Yervant Zorian, TTTC Chair, zorian@lvision.com
Southwest Test Workshop Sets Another Record!
Southwest Test Workshop started in 1990 as a small, regional
meeting of test professionals who gathered to discuss general IC test topics.
After three years of following that format the organizers, recognizing a need
for a meeting focused on wafer testing, asked TTTC to approve a change of
mission the rest is history. Workshop attendance grew to 148 that year, 238 the
next year, and 288 last year.
This year, the workshop, which was held at the Princess Resort
Hotel in Mission Bay, near San Diego, California, June 1-4, educated and
entertained 400 enthusiastic participants.
In spite of its dramatic growth, SWTW still tries to maintain its
workshop identity rather than become a formal symposium or conference. For
example, the organizers believe that half the value of a technical meeting is
in the informal interactions, so they devote a sizable portion of the workshop
to long breaks and numerous social activities, such as a Mexican Fiesta, a
Hawaiian Luau and three hosted cocktail receptions. Also, recognizing that
unrehearsed panel discussions often reveal issues that would be too politically
incorrect to present in a formal setting, SWTW '97 had four panel or open
discussion sessions, all actively involving the audience. The initial Sunday
evening panel discussion was video-taped. The tape was distributed to all
attendees at the conclusion of the workshop.
SWTW's regular technical program began on Monday morning with a
session on RF probing. One presentation concerned probe activities as evaluated
by an ATE vendor. A mini-tutorial described the relationship between RF
terminology and the high-frequency testing vernacular. After the morning break,
the session dealt with the automatic probe-mark inspection features now
included by the three major prober manufactures. Each manufacturer described
their APM features and performance parameters, and then, to keep them honest,
members of the audience shared their actual experiences in an open discussion.
Monday afternoon featured a variety of elective group activities designed to encourage informal discussions. The hotel's 18-hole miniature golf course entertained "golfers" in a putters-provided, shotgun-start tournament. Other attendees took a 2-hour San Diego sightseeing-trolley tour that included Old Town, downtown and other city sites, the wharf area, Coronado Island and Balboa Park. Another group took a San Diego Harbor Cruise and toured one of the largest recreational harbors on the West Coast, plus the fishing fleet, North Island Naval Air Station, and the US Navy fleet in dry dock. On Monday evening, all attendees enjoyed a Hawaiian Luau buffet dinner around the hotel pool.
The first session Tuesday morning discussed the
issues of docking a many-hundred-pound test head with an even heavier prober,
while requiring accuracies of a fraction-of-a- mil and gram. The first
presentation covered the problem of conventional and newly developed interface
solutions. The next two presentations provided detailed models and error-budget
analysis as they relate to the interface itself and probe-card requirements.
After the morning break, there were four presentations on high-temperature
probing. These included an overview of some Sematech activities, a new
matched-expansion probe card, an analytical model for probe-card performance at
elevated temperature, and measured thermal-probe chuck performance.
Multi-die probing was the topic of the first session after lunch.
Advances in cantilevered probe cards and newer probe technologies have found
increasing applications in multiple die testing, so three microelectronic
manufacturers presented their experiences with different probe technologies.
Then, for the first time, the SWTW had two parallel breakout sessions in the
afternoon. Each session had a panel which began the discussion and then the
attendees, who had been enticed with cookies and soft drinks, were encouraged
to share their views. The topics were probe operations and new probe
technologies.
Tuesday evening, attendees enjoyed a formal dinner banquet which
included awards and an after dinner speaker. Our after dinner speaker discussed
the issues and potential solutions for a completely automated, lights-out,
probe test operation. Then awards were given for the best presentation, best
data, lowest miniature-golf score, worst sunburn, and the infamous SWTW award
for the poorest-disguised sales pitch.
Wednesday morning featured a general session entitled Probe
Potpourri. Three presentations covered: probe-needle materials; the roadmap to
50-micron probe pitch; and advanced technology in cantilever needle-probe
cards. After the morning break, there were three excellent presentations on new
probe-card technologies. The workshop adjourned Wednesday at noon.
Southwest Test Workshop 1998 is scheduled to begin with a tutorial Sunday afternoon, May 30,1998. Please contact the TTTC Office, EdDor@aol.com, if you would like to be on the mailing list for SWTW.
Article
by Bill Mann, william.mann@nb.rockwell.com
VTS '97 marks 15 years
In Monterey, California, recently, IEEE VLSI Test Symposium
celebrated fifteen years of growth from a small workshop to an international
symposium where test and design professionals from both industry and academia
debate key issues in testing. The 1997 VTS, sponsored by TTTC, attracted more
than 300 attendees from both the electronics industry and the world's leading
universities.
The rapidly increasing complexity of microelectronic components
combined with high-density packaging have made it difficult and costly to
adequately test electronic systems using established methods. And industry
forecasters warn that the situation will intensify with increased use of
embedded cores and high-density packages.
Clearly the industry needs innovative advances in test,
design-for-test, and diagnosis methodologies. The VTS'97 technical program
aptly responded to these demands with 62 paper presentations, eight panel
sessions, five tutorials, a keynote address and an invited talk. Spirited
discussions on topics novel to VTS, such as embedded-core testing, on-line
test, thermal and elevated voltage stress testing, and design validation,
augmented animated exchanges on scan test, mixed-signal test, delay test,
current testing (IDDQ ), fault simulation and other more established
subjects.
Complex systems-on-chip, a gleam in the eye of developers for
many years, finally are becoming a commercial reality. Core-based
systems-on-chip received extensive coverage. The topic started with a popular
tutorial, by Yervant ZORIAN, LogicVision and Sujit DEY, NEC. The tutorial
presented the basic concepts and the best current practices in testing embedded
cores and systems-on-chip. Then, in the opening session, Dataquest's Gary SMITH
projected the future of systems-on-chip technology in an invited address.
Keynote speaker Gadi SINGER, General Manager of Design and Test Technology at
Intel, effectively addressed the test complexity issue.
The first technical paper session continued the topic with a set
of presentations on novel embedded-core test solutions. Later a dedicated panel
discussion revealed the common needs of industry companies for effective
methods to design and test systems-on-chip. Finally, a IEEE P1500 Study Group
meeting heard proposals for several embedded-core standardization approaches.
The state-of-the-art in defects and faults was discussed in a
popular panel session about recent Sematech experiments on the comparative
effectiveness of functional, scan, IDDQ, and delay-fault testing methods. The
panel discussion will be reported in an upcoming issue of IEEE Design &
Test of Computers as a Round Table discussion article.
The challenges facing the VLSI ATE industry was another new topic
for VTS. In a spirited panel session, panelists from the IC manufacturing,
design, and ATE industries, examined the consequences of the continuing
decrease in pin-to-gate ratio. Among other questions, the panel discussed how
future ATE might address throughput limitations while testing multi-million
gate chips.
This year, the VTS social program included a visit to the
Monterey Aquarium, a tour of the Carmel area, and an informal dinner at a local
winery. After the dinner, VTS General Chair Yervant Zorian, presented awards to
the volunteers who contributed to the success of VTS'97.
Commenting on VTS's growth into one of the headline meetings in
test, Zorian remarked, "VTS is not a stand-alone event. It complements the
numerous other TTTC technical meetings held throughout the year. However, it is
quite unique, I think. It's uniqueness lies in the combination of two aspects:
the selection of state-of-the-art topics and the participation of key test
experts in an informal and very inter-active setting." The quality of
technical papers combined with the social interaction provided by panels and
social events are keys to attracting the experts year after year.
Zorian stressed the need for keeping close to customers, "We
are very sensitive to feedback from our attendees, since we look at the
symposium as a service to a limited community of test experts." The task
of producing an outstanding meeting year-after-year never ends. "During
its first 15 years, VTS had sharp growth in the quality of its offering. Our
most challenging problem now is to keep surpassing the high quality
expectations the symposium is setting year after year."
VTS's 15-year success record and its ever-increasing popularity among test and design professionals is solid evidence that the symposium's strategy meets a community need. It is also a tribute to the VTS committees over the years. Their efforts have made VTS a place to innovate, explore, and demonstrate creativity in solving test problems.
Article by Bozena Kaminska, OPCOMM, and Ed Thomas
THERMINIC Workshop to visit the Cote d'Azur
THERMINIC
1997, the International Workshop on Thermal investigations of ICs and
Microstructures, will be held in Cannes, France, on the Cote d'Azur, September
21-23, 1997. The workshop is sponsored by TTTC, in cooperation with the
THERMINIC CP940922 Copernicus, the BARMINT 8173 ESPRIT Projects, the European
Test Technology Technical Committee, and SPIE, the Society of Photo-Optical
Instrumentation Engineers.
The THERMINIC Workshops bring leading professionals in the field
together to discuss the essential thermal questions of microelectronics and
microstructures. These questions are becoming more and more crucial with
increasing element density due to deep-submicron downscaling of integrated
circuits, necessitating thermal simulation, monitoring and cooling. The high
element density of MCMs and microsystems raise new thermal problems to be
solved in the near future. Thermal effects on the other hand can be used as the
basis of sensors or other functional structures.
The first THERMINIC Workshop was held in Grenoble in 1995, where
about 90 participants from Europe, USA and Japan attended 43 presentations. The
second THERMINIC Workshop was held last year in Budapest.
This year the Program Committee has accepted 28 contributions for
oral presentation and 33 for poster presentation. The main topics for
discussion are:
<> Thermal and Temperature Sensors and Actuators
<> Evaluation of Thermal Measurements
<> Thermal and Electro-thermal Modelling and Simulation
<> Temperature Mapping
<> Measuring Thermal Material Parameters
<> Thermo-mechanical Effects
<> Thermal Modelling and Investigation of Packages
<> Reliability Issues
An informal proceedings of the papers will be distributed to
attendees. Later, two journals, The Journal of Sensors and Actuators
A-Physical, and iThe IEEE Transactions on Components, Packaging, and
Manufacturing Technology, will publish special issues based on the workshop.
A product exhibition will be held during the Workshop. The
exhibitors will also participate in a vendors' presentation session.
The Workshop will be held at the SOFITEL-Mediterranee hotel in
Cannes on the Cote d'Azur, a world famous resort area. Cannes is served by the
airport of Nice which is 40 minutes distance by shuttle bus and by the local
airport of Cannes-Mandelieu, just 10 minutes away. Cannes may also be reached
by highway and by train. The Sofitel Hotel, on the westernmost point of the bay
of Cannes, is bordered by beaches of fine sand and overlooks the yacht harbour
and the Croisette.
The General Chair of THERMINIC 1997 is Bernard COURTOIS, TIMA
Grenoble/France. Marta RENCZ, TU Budapest/Hungary, is Vice-General Chair and
Vladimir SZEKELY, TU Budapest/Hungary is the Program Chair.
For more information on the workshop, contact Bernard Courtois, E-mail: bernard.courtois@imag.fr
or visit the workshop Web
site at:
http://tima-cmp.imag.fr/confs/therminic97/therminic97.html
Article submitted by Bernard Courtois
Fourth MCM Test Workshop
Reconvenes
in Napa Valley
MCM Test IV, the fourth in a series of advanced technology
Workshops that explores the latest solutions and trends in testing MCMs, will
give designers, test engineers and researchers an excellent chance to get an
in-depth view of the latest MCM test practices and design techniques. The
workshop will be held on September 14-17, at the Inn at Napa Valley, Napa,
California.
Since the cost and complexity associated with testing and
diagnosing MCMs remain among the most critical issues in MCM manufacturing
today, the workshop will present numerous case studies on MCM test applications
and substrate testing. The workshop will also cover the latest BIST,
Boundary-Scan, and thermal-based solutions. MCM Test IV Workshop is sponsored
by International Microelectronic And Packaging Society and TTTC. For further
information, please contact General Chair, Yervant Zorian at
zorian@lvision.com.
Article submitted by Y. Zorian
TEST TECHNOLOGY IN ASIA
Akita will host 1997 Asian Test Symposium
Akita, a small, charming city on the northern coast of Japan, is the site of the sixth Asian Test Symposium. The city, blessed with four beautiful seasons, is situated near some of the most beautiful lakes, national parks, and volcanic hot springs in Japan. Akita is also known for its delicious rice, Sake, the Kanto (Lantern) festival, and friendly people.par
At
ATS, researchers and engineers from around the world, but especially from Asia,
explore the state-of-the-art and trends in test and design for electronic
circuits and systems. This year ATS has received 99 papers for regular and
special topic sessions from 18 nations2E
The 1997 symposium will be held November 17-19 at the Akita
Castle Hotel. The two-and-a-half day technical program will consist of 15
regular sessions and three special sessions. Fifty-five papers will be
presented in the regular sessions covering most of the key areas in testing.
Featured are special sessions on Case Studies for DFT Techniques in
Japanese Industry and Beam Testing Techniques in Japan. Dr. Vinod AGARWAL,
LogicVision, will give a keynote address entitled Embedded Test and
Measurement is Critical for Deep Submicron Technology.
Symposium attendees can explore Akita in an optional half-day
tour which will visit Kakunodate, called Little Kyoto, and the Hideyoshi
Sake Brewery. The old streets of Kakunodate remain dotted with Samurai Houses
creating a serene atmosphere. Hideyoshi Sake Brewery produces exceptional sake
by using famous Akita rice, clear water and superior brewing techniques.
You will surely enjoy the nature and the culture of this area as well as the technical activities at the symposium. We look forward to meeting you in Akita, Japan!
For more information, see:
http://ats97.cs.ehime-u.ac.jp/
Article by Teruhiko Yamada, Meiji University
Bridging fault and IDDQ testing in China
More than three decades ago, the stuck-at-fault model was
introduced and has been employed to represent faults in digital circuits. In
general, the stuck-at fault model has worked satisfactorily for TTL and nMOS
devices. A number of algorithms and techniques have been developed for test
generation using this model. Even if the model can not cover some of important
defect models, it still has been convenient and therefore is widely used.
In recent years, CMOS has emerged rapidly as the dominant
technology in the areas of computer systems. In this technology the stuck-at
fault model does not well represent actual faults. In ULSI circuits,
especially, bridging faults and transistor stuck-on faults may account for more
than 40% of defects. Increasingly, these fault models have become more and more
significant with the density of the circuits in a chip higher and higher.
In Shanghai China, several projects have been granted in the area
of testing for bridging faults by using IDDQ techniques. One research
project, being conducted at Shanghai University (recently formed by merging
Shanghai University of Science and Technology and Shanghai University of
Technology) is supported by the AM Foundation (Applied Materials, Inc., USA).
The research team led by Professor Shiyi XU of Shanghai University is
developing some new techniques for testing bridging fault in CMOS circuits.
A bridging fault may occur between any two electrical nodes,
whether they belong to one layer or to different layers. A manufacturing defect
or a wear-out mechanism like electromigration, may cause a bridging fault with
significant resistivity. From the logical point of view, bridging faults may be
divided into two classes:
1. AND-bridging (A wire-AND occurs when two-or-more nodes connect together);
2. OR-bridging (A wire-OR occurs when two-or-more
nodes connect together)
From the manufacturing technical point of view, bridging faults
also may be grouped into two other classes:
1. Non-feedback bridging fault (Bridging between two-or-more logic elements without a feedback loop);
2. Feedback bridging
fault (Bridging between two logic nodes, creating a feedback loop).
The number of bridging faults in a circuit could be much greater
than the number of single stuck-at fault in the same circuit. Therefore,
testing for the bridging faults could be much more difficult than testing for
single stuck-at faults. IDDQ technology is now being used as an efficient
tool to test for bridging faults. The Shangai University project has had some
initial results that show a promising future in testing for bridging faults by
using IDDQ technology. It is expected that more results will developed in
the near future.
This article was written by the Fault Tolerant Computing
Research Team, Computer Science Department, Shanghai University
Submitted by Professor Shiyi Xu, Shanghai University
ISSUES IN TEST
Should we worry about pennies for power?
Professor Cheng-Wen Wu of the National Tsing Hua University in
Hsinchu, Taiwan, thinks tester manufacturers and users should pay more
attention to power consumption during testing.
Professor Wu says, "Many people believe that power
consumption affects overall manufacturing and operating costs higher power
means greater silicon area, shorter life, lower quality and reliability, more
difficult in heat removal, etc. However, few seem to be seriously concerned
about power consumption during testing. Consider that the power to drive the
300-plus VLSI testers at Intel, in support of a throughput of more than 50
million CPU chips per year, is more than 8 megawatts, enough to supply a small
city. Not only is test equipment Intel's greatest capital expense, tester power
is becoming an issue." With 30% of product cost due to testing, it pays to
look everywhere for savings.
Not a person to leave an issue un-addressed, Wu has organized a
panel session to discuss the issue at the annual VLSI Design/CAD Symposium
in Taiwan. The symposium, which attracts more than 500 attendees from local
universities, research institutions, and industries each year, is an important
meeting for Asia's test engineers and researchers. Wu's panel, entitled What
Do You Care About Power Consumption During Testing? will be held on August 22,
1997, at Sun-Moon Lake, Nantou, Taiwan. (NOTE: VLSI Design/CAD Symposium is
not sponsored by TTTC.)
The panel will address a number of questions about power
consumption during testing. First and foremost -- should we worry about it? But
also, does power consumption affect test quality? Are good chips damaged during
testing which usually intentionally involves high transition activity? Is the
electricity bill an issue? Are low power and high testability competing goals
for CMOS? Is there any way out? Last but not least, how can we accurately
measure worst-case power consumption of a low-power device?
What's your opinion? Is power consumption really an issue in test?
Article based on material supplied by Cheng-Wen Wu,
National Tsing Hua University, Hsinchu, Taiwan
Crete hosts 3rd IEEE International On-Line Testing Workshop
The 3rd IEEE International On-Line Testing Workshop was held on
July 7-9 1997 in Crete, Greece. Sixty-eight participants from 21 countries
attended and participated actively in the workshop. For the final program 45
technical papers from 20 countries were selected and presented in a framework
of 11 sessions:
<> System-level Reliability
<> Self-Checking Data Paths and Controllers
<> Case Study : The AE11 Fail-Stop Controller
<> Sensors/Detectors for On-Line Testing
<> Analog and Mixed Signal On-Line Testing
<> Current Monitoring
<> Fault Tolerant and Fail-Safe Systems
<> Scan-Path and Boundary Scan for On-Line Testing
<> FPGA Implementations <> BIST
<> Self-Checking Circuits
This year the workshop emphasized enhanced communication between
industry and academia. To this end, the workshop featured a case study session
devoted to an important project from the automotive electronics industry
concerning the development of a fail-safe processor for control of critical
automotive functions. The new control processor incorporates self-checking
techniques, BIST and on-line IDDQ testing on a single IC to achieve a low-cost,
highly reliable design. This first-time achievement is an important step
forward in economical on-line testing. A panel, organized in the same context, On-Line
Test - Academic Research and Industrial Needs: How Do They Correlate?, was also
greatly appreciated by the attendees.
An important field of investigation, On-Line Monitoring of
Reliability Indicators, was introduced by TTTC's On-Line Testing TAC when
it was first formed in 1995 and has been a workshop topic ever since. Two
sessions, with papers on on-line monitoring of current, temperature, timing,
and clock signals, were dedicated to the topic this year.
The workshop's industrial presentations, as well as the advanced
developments reported from academia, contributed to a high quality program that
created strong interactions among the participants.
The workshop social program gave attendees an opportunity to
visit the famous Knossos Palace and the Archaeological Museum of Heraklion. All
participants also greatly appreciated a Greek Barbecue Night with local food
and folkloric music and dances. A collection of workshop photos can be found
at: www.eng.usf.edu/CMR/athan/ieeeioltw.html
Article by Michael Nicolaidis, General Co-Chair
___________________________________________________________________________________
ITC to offer 16 Test Tutorials
Testing continually attracts new practitioners who want to learn the basics. Experienced hands sometimes need to broaden their knowledge or increase their depth in this dynamic field. ITC Test WeekTM meets these needs by offering 16 tutorials day-long classroom sessions taught by recognized experts.
Along with the tutorials, there will be a special
seminar offered on Sunday, Nov. 2. The seminar is part of a three-part series
of events on Test Economics: Saturday, Tutorial 6; Sunday,in Test
Economics Seminar; Wednesday and Thursday, The 5th International Workshop
on the Economics of Design and Test. The tutorials and the seminar require a
separate registration fee.
ITC Tutorials Saturday, Nov. 1, 8:30 am - 4:30 pm
1. Testing Complex System-On-Silicon Chips, B. Koenemann,
K. Wagner
2. Digital Test Principles I: Test Requirements and Test Pattern
Generation, E. McCluskey
3. Synthesis of Self-Testable System-on-chips , Y. Zorian, H.J.
Wunderlich
4. Boundary Scan and Other 1149.x Standards, B. Bennetts, C. Maunder
5. Metrics, Techniques and New Developments in Mixed-Signal Testing, G.
Roberts
6. Cost of Test! ... What can I do about it?, G. Perry
7. Testing Memories: Basic Concepts and Algorithms, A. van de Goor
8. Error, Fault, and Defect Diagnosis: A Detective Story, M.
Abramovici, R. Aitken
ITC Tutorials Sunday, Nov. 2, 8:30 am - 4:30 pm
9.
Digital Test Engineering, R. Huston
10. Digital Test Principles II: DFT and BIST, E. McCluskey
11. IDDQ Testing for Efficient Detection of CMOS IC Defects and Faults0
,
R. Aitken, J. Soden, K. Baker
12. Memory Testing: Advanced Concepts, including DFT and BIST, A. van
de Goor
13. Test Synthesis: The Practicality of DFT, K.T. Cheng, J. Beausang
14. An Introduction to Successful Board-Test Strategies, S. Scheiber
15. MCM Testing Strategies, Y. Zorian
16. BIST Applications, R. Sedmak
17. Test Economics Seminar, T. Ambler, M. Abadir.
Complete descriptions can be found in the ITC Advance Program. If
you have not received a copy, please contact Pam WAGNER, Tel: (202) 973-8665.
E-mail: itc@courtesyassoc.com
ITC Tutorials are sponsored by TTTC. International Test Conference is sponsored by the IEEE Computer Society TTTC and the IEEE Philadelphia Section.
________________________________________________________________________-----------------------------------------------------------------------------
EDITORIAL POLICY
This newsletter is the informal publication of the IEEE Computer
Society Test Technology Technical Committee. We will publish all appropriate
material although editing may be necessary to meet space or typographical
constraints. Articles are not refereed unless so noted. Opinions are those of
the contributors and are not necessarily the opinions or positions of TTTC, the
IEEE, or the IEEE Computer Society.
Contributors who wish to have their employers name included with
their byline must specifically request it with their contribution. TTTC
Newsletter is not in any way responsible for any issues that may arise with the
employer or others as a result of a contribution to the newsletter.
Editor and Publisher: Ed Thomas
Associate Editor - Mike Keller
Associate Editor, D&T magazine - Don Lenhert
Associate Editor - Europe: Ian Dear
Associate Editor - Asia: Teruhiko Yamada
SEND CONTRIBUTIONS TO:
Ed Thomas, Editor, TTTC Office, PO Box 629, Hollidaysburg, PA 16648 USA. Tel: (814) 941-4669, Fax: (814) 941-4668.
E-mail: eddor@aol.com
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