Test Technology Newsletter
July - September, 1998
The Newsletter of the Test Technology Technical Committee of the IEEE Computer Society
The move to very deep sub-micron technologies has raised test challenges into the limelight. From the 1997 SIA road maps to the analysts' reports, the impact of test on the chip making industries is considered enormous. TTTC efforts to analyze this impact and address its challenges have been numerous in the past few months.
The period from April to July has always been a prosperous season for TTTC activities, but this year more than ever, the period was packed with almost overlapping workshops, standards meetings, tutorials and educational activities. Almost all TTTC activities in this period were very successful. Several articles in this Newsletter will inform you more about the specifics of these activities. The larger events of this period, DATE, VLSI Test Symposium, South West Test Workshop, and European Test Workshop, all attracted record number of participants.
The educational role of TTTC has also taken a sharp turn upward in this period. The increasing efforts to provide solid background in key test technology domains by the Tutorials Group motivated several workshops to start tutorials. Examples are ETW, MCM Test, and Memory Test workshops. Test education has also been increasingly addressed by our publications. IEEE Design & Test of Computers recently provided excellent coverage on the topics of microprocessor test, FPGA test, thermal test and test for advanced packaging technologies. Future issues of D&T plan to go even further with articles on the background knowledge on emerging test technology topics, such as testing huge embedded memories, MEMs, and on-line test for VLSI.
The standards working groups too continued their active efforts in searching for commonly acceptable solutions in a number of areas. The IEEE P1500 group has started to put together the remaining pieces of the puzzle for a standard core test-access solution. If you, or your company, have not yet taken part and have not influenced this or other TTTC standards, it is not late to join in, to assure that your views are considered, and to actively contribute to the outcome.
Even though it is larger than usual, this Newsletter provides only partial coverage of all our activities. There are so many interesting and important things happening under the TTTC umbrella that it is difficult to report all of them in the Newsletter. For more comprehensive coverage about our technical meetings, please consult your TTTC 1998 Monthly Planner (contact the TTTC office, if you did not receive it). I would recommend too that you carefully check the ITC Test WeekTM Advance Program and carefully consider all the paper sessions, tutorials, and workshops before you plan your trip to Washington (check the TTTC Web Site, if you did not receive the program). Also, please make sure you check the list of TTTC meetings during ITC Test Week on page 1.
Your efforts are valuable to the rest of the test community. It is impossible for each one of us to personally participate in all the activities that we are interested in. Please share information about your activity with your colleagues through the pages of this Newsletter. This Newsletter is the result of months of work by many members like you. I would like to take this opportunity to thank each contributor to this expanded issue.
Yervant Zorian, TTTC Chair
Oct. 19,5:00pm - 7:30pm, ExCom
Oct. 20, Noon-1:30pm, European Group (ETTTC)
Oct. 20, 5:30 - 7:00pm, Standards Group (TTSC)
Oct. 21, 7:00 - 9:00am, Meetings Group (TMRC)
Oct. 21, Noon - 1:30pm, Technical Activities Group
Oct. 21, 5:30 - 7:00pm, Tutorials Group
Oct. 22, 7:00 - 9:30am, OpCom
Please check at the registration desk at ITC'98 for any late changes in scheduling.
Computer Society presents Harry Goode Memorial Award to Vishwani Agrawal
In a ceremony held during a society meeting on June 3, 1998, in Quebec City, Canada, the IEEE Computer Society presented the 1998 Harry Goode Memorial Award to Dr. Vishwani D. Agrawal. The prestigious award recognizes Dr. Agrawal's outstanding contribution to the information processing field and especially his innovative contributions in the area of electronic testing.
Dr. Agrawal's work on digital testing has been widely used in the industry and by other researchers. His research, conducted with many colleagues at Lucent Technologies Bell Labs and at various universities, includes random test generation, fault sampling methods, reject ratio determination from fault coverage, statistical fault analysis (Stafan), a probabilistic testability measure (Predict), directed-search and stimulation-based methods for test generation, neural network and graph-based methods for test generation, a method of partial scan design for testability, the test machine embedding concept of finite state-machine synthesis, distributed computing methods for sequential circuit test generation, sequentially untestable fault theorems, and rated and variable methods for path delay testing of sequential circuits.
Dr. Agrawal is currently a Distinguished Member of the Technical Staff in the Computing Sciences Research Center of Lucent's Bell Labs at Murray Hill, NJ. In 1978, Agrawal joined Bell Labs to pursue research on electronic testing. He has co-authored over 200 papers and four books: Test Generation for VLSI Chips, 1988; Unified Methods for VLSI Simulation and Test Generation, 1989; Neural Models and Algorithms for Digital Testing, 1991; and Concurrent and Comparative Discrete Event Simulation, 1994. Since 1991, he has been an honorary Visiting Professor of Electrical and Computer Engineering at Rutgers University in New Jersey where he regularly collaborates with faculty and students on teaching and research related to testing.
In 1990, Dr. Agrawal founded the Journal of Electronic Testing Theory and Applications (JETTA), the only archival journal in testing. He has served as Editor-in-Chief since the journal's inception. He is also Consulting Editor for the Frontiers in Electronic Testing series of books published by Kluwer Academic Publishers, Boston. In 1985 he co-founded the International Conference on VLSI Design under the sponsorship of India's Department of Electronics and the VLSI Society of India. Under his leadership, this meeting has become a prominent and prestigious conference in the Indian region.
>From 1985 to 1987, Dr. Agrawal served as Editor-in-Chief of IEEE Design and Test of Computers magazine. In 1987-89, he served on the Board of governors of the IEEE Computer Society. In 1993, he chaired the Fellow Evaluation Committee of the Computer Society. He was the Program Chair for the Fourth Asian Test Symposium and has served on the program committees of many conferences in the areas of design and test, including International Test Conference, Design Automation Conference, and European Test Conference. Dr. Agrawal is an IEEE Fellow, a Fellow of the Institution of Electronics and Telecommunications Engineers (India), a Member of the ACM and of the VLSI Society of India. He has received many awards, including the Computer Society's Outstanding Contribution Award, Meritorious Service Award, and Golden Core Member Award; the University of Illinois Distinguished Alumnus Award and five Best Paper Awards,
Dr. Agrawal received his BSc degree from Allahabad University, India; BE degree from Roorkee University, India; ME degree from the Indian Institute of Science, Bangalore , India, and PhD degree from the University of Illinois in 1960, 1964, 1966 and 1971 respectively. In 1970-71, at Automation Technology, Inc., he acquired an interest in testing while working on the ILLIAC IV computer project. Otherwise his early interests concerned microwaves and antennas. Dr. Agrawal has worked at the University of Illinois; EG&G, Inc., Albuquerque, New Mexico; Indian Institute of Technology, New Delhi, India; and TRW, Redondo Beach, California. In 1979, he co-authored the paper, Design of a Dichroic Cassegrain Subreflector, which won the Best Paper Award of the IEEE Transactions on Antennas and Propagation.
The Harry Goode Award was initiated in 1964 by the American Federation of Information Societies (AFIPS) in recognition of Mr. Goode's invaluable contributions to the information processing societies. One of the first scientists to fully comprehend the powers of computers, Mr. Goode formulated many principles of system engineering and developed techniques for the design, analysis and evaluation of large-scale systems. He was instrumental in such early systems as the Typhoon and Whirlwind computers. He also advanced information processing science through teaching at the University of Michigan and his many publications on statistics, simulation and modeling, vehicular traffic control, and system design. He co-authored the first book on System Engineering. Mr. Goode was a member of the IRE, now the IEEE. On the dissolution of AFIPS in 1990, the IEEE Computer Society agreed to assume responsibility for the continuation of the award. The award, which includes a bronze medal and $2,000, is awarded annually to encourage further development of the field and to acknowledge and honor outstanding contributions to the information sciences. Previous awardees include such distinguished computer pioneers as Howard Aitken, George Stibitz, John Mauchly, J. Presper Eckert, Grace Hooper, Seymour Cray, Gordon Moore, Robert Noyce, Herman Goldstine, Gene Amdahl, and Carver Mead.
TTTC starting directory of member home pages
The Test Technology Technical Committee is building an experimental Home Page Directory for its membership. If you have a home page which might be useful to other TTTC members, and you want it to be included in the directory, please e-mail the Uniform Resource Locator (URL) for this directory to:
west@ieee.org
To facilitate the inclusion of your home page in the directory, please use the phrase:
tttc home page directory
as the subject of the e-mail, and put exactly three lines in the body of the e-mail message. Use the following sample as a model:
http://www.someplace.somewhere/public/you
Furshlig, B, Ph. D., U. of Hard Knocks, Bronx, N.Y.
CAE, ATPG, horsemanship
These three lines are:
The complete URL of your home page
Your name, title, and affiliation
Your main research interests
Following is a short FAQ list:
What is the TTTC Home Page Directory?
It is a listing of publicly accessible World Wide Web homepages of TTTC members.
What should the TTTC Home Pages contain?
Information the submitter wants to be made available to TTTC members, as well as the world at large. Included might be technical publications, interesting pointers (URLs), research interests, open questions, biographical information, philosophical positions, and other things at your discretion. TTTC obviously CANNOT take any responsibility for the contents of the home pages listed in the directory, and makes no promise that all URLs submitted to the directory will be included. One item that must be included in every home page is whose home page it is and how to contact him or her. If this information is not immediately apparent in the home page itself, then the URL may not be included in the directory.
Is there an example of a home page?
Yes. The URL for the directory itself is:
http://www2.san-jose.ate.slb.com:65080/tttc
Visit it to see home pages that are already installed.
Can anyone get at the information in my home page?
Yes. Anyone who has WWW access could view your page, so don't send a URL if your home page contains proprietary or private material. You could, of course, create another home page explicitly for public access.
Is there any guarantee that a URL in the TTTC Home Page Directory actually points to an accessible web page?
No.
If I send a URL, will it definitely be included in the new TTTC directory?
No. Pages that appear tasteless, obscene, or irrelevant will not be included. Directory entries may be excluded or removed for any reason or, for that matter, for no reason at all. This is an experimental service and no guarantees of accuracy, consistency, or relevance are either expressed or implied.
If I send a URL, can I later get it removed from the directory?
Yes, but it will not happen immediately. It could take several days or more.
How permanent is this directory?
This Home Page Directory is experimental. It may change its URL or vanish entirely, based on experience.
What is the URL for the TTTC Home Page Directory?
http://www2.san-jose.ate.slb.com:65080/tttc
A link to this directory will be installed in the TTTC Web Site.
Burnell West
Changing Positions/Addresses/E-mail
Bill Bruce has relocated. His new coordinates are: Motorola, MS: F-30B, 5918 W. Courtyard Dr., Suite 330, Austin, TX 78730. Tel: (512) 794-4800. Fax: (512) 794-4235. E-mail: bruce@udsl.sps.mot.com
Effective Sept.1, Krishnendu Chakrabarty can be reached at: Department of Electrical and Computer Engineering, Duke University, Box 90291, 130 Hudson Hall, Durham, NC 27708. Tel: 919) 660-5244. Fax: (919) 660-5293. E-mail: krish@ee.duke.edu
Ramesh Karri, TTTC Vice Secretary, is relocating. His new coordinates are: Associate Professor, Dept of EE, Polytechnic University, Brooklyn, NY 11201. Tel: (718) 260-3596. Fax: (718) 260-3906. E-mail: ramesh@isaacs.poly.edu
Bruce C. Kim, TTTC Vice Chair, Awards, has accepted the position of Assistant Professor, Department of Electrical and Computer Engineering, Michigan State University, 2120 Engineering Building, East Lansing, MI 48824-1226. His new electronic coordinates are: Tel: (517) 432-2630. E-mail: kimb@egr.msu.edu
Fabrizio Lombardi has accepted a position at the Department of Electrical and Computer Engineering of Northeastern University, 110 Forsyth Street, Building 309 Dana, Boston, MA 02115. His new electronic coordinates are:, Tel: (617) 373-4159. Fax: (617) 373-8970. E-mail: lombardi@ece.neu.edu
Prab Varma has accepted a position a Veritable, 1688 Montalto Drive, Mountain View, CA 94040. Prab can be reached at: Tel: (650( 964-5059. Fax: (650) 969 5914. E-mail: prab@veritable.com
Ken Wagner has accepted the position of Manager, Design Flow Group at Siemens Microelectronics, Inc., San Jose, CA. Ken can be reached at: Tel: (408) 895-5160. Fax: (408) 895-5020. E-mail: kenneth.wagner@smi.siemens.com or k.wagner@computer.org
Keep in touch! Let your colleagues know where you can be reached. If your position, address, e-mail, etc. are changing, please let us know. E-mail your change to EdDor@aol.com.
At their meeting early this year, the Computer Society Board of Governors voted by acclamation to thank Test Technology TC volunteers for their "notable contributions over these many years to the test technology technical field." In a letter to TTTC conveying the CS recognition, CS President, Barry Johnson, commended TTTC's organizers and congratulated them on the occasion of the TTTC Twentieth Anniversary, which is being celebrated this year. Johnson' s letter, addressed to TTTC Chair Yervant Zorian, also recognized the "generous contributions of (TTTC) volunteers to the success of this important TC over the past 20 years" and added his "sincere appreciation to all (TTTC) committee members and our best wishes for continued success."
ITC'98: Test WeekTM program targets core challenges
In Washington, DC, from October 18-23, test and design professionals from around the world will gather during ITC Test Week, the annual test event that sparks new directions in technology. On October 20-22, at International Test Conference, the cornerstone event of ITC Test WeekTM, industry and academic professionals can take advantage of numerous opportunities to join with their colleagues in technical paper sessions, panels, workshops and special seminars on embedded cores and MEMS. Here they can also experience the most extensive exhibition of the latest in test hardware, software and services, and attend ITC Exhibitors Forum where leading companies present and explain their new products.
ITC's program is full of hot topics in testing and design-for-test. In addition to embedded cores and MEMs, other topics gaining momentum in the program include: issues that are emerging as digital speeds approach and exceed 1GHz; what IDDQ failures really mean in today's landscape; and, new test and diagnostic methods for advanced microprocessors. At ITC'98, IC professionals can get up-to-speed on today's most important design and test topics.
Two days of informative and educational tutorials, organized by TTTC, initiate Test Week on October 18-19. The 17 educational presentations, ranging from the theoretical to the practical, are targeted to those who are new to testing, as well as to experienced practitioners who want to increase or broaden their knowledge. This year, in addition to the traditional foundations of test technology, such as BIST, boundary scan, test synthesis, IDDQ test, mixed-signal test, digital test, memory test, board test, diagnostics, MCM test and test economics, the tutorial program will offer new tutorials on: performance verification, functional design verification, deep-submicron challenges for mixed-signal, and jitter analysis.
Concluding Test Week on October 22-23 are three workshops: Embedded Core Test, Production Test Automation, and Design Verification of Microprocessors. Running concurrently, the workshops offer a venue for professional discussion and exchange on topics of importance to the test community. The workshops are sponsored by TTTC.
The ITC '98 technical program will focus extra attention on two topics of special current interest: embedded core testing and MEMS testing. In addition to coverage in a number of technical papers during ITC's paper sessions, core testing will be addressed in an invited paper during ITC's plenary session, in a special seminar, and in the aforementioned workshop. Another special seminar, in addition to the tutorial mentioned above and a number of technical papers, will cover the MEMS test topic.
Test professionals who are responsible "on the line" in industry should check out the two new lectures in ITC's Lecture Series: New Technologies in Wafer Probe, and Partial-Access Board Test Technologies. ITC's Lecture Series follow a tradition of presenting practical information that works today for engineers who need solutions now.
As if all-of-the-above wasn't enough, ITC also will feature ten panel sessions. These sessions, promising the panel/audience give and take that ITC participants have come to expect, including a smattering of verbal fireworks, will include the following:
The Reality of the SIA Roadmap
The Battle between Quality and Yield
System-on-Chip Test
Can BIST Replace ATE?
Can Flying Probers Replace Traditional Methods?
In addition to its technical programs and exhibits, ITC offers test and design professionals numerous opportunities to meet with colleagues at the many ancillary meetings, complimentary breaks and receptions, luncheons and other social events.
To request a copy of the 1998 ITC Advance Program with full conference details, highlights of Test Week Activities, and registration information, please contact us. Here's how:
World Wide Web: http://www.itctestweek.org
Tel: +1 202.973.8665 or fax at +1 202.331.0111
e-mail: pwagner@courtesyassoc.com
>From information supplied by ITC
1999: ITC moving to Atlantic City
The organizers of International Test Conference recently announced that they will hold the 30th implementation of the test industry's premier technical meeting at the new Atlantic City Convention Center in Atlantic City, New Jersey, USA. The conference, held in Washington, DC, USA for the last five years is moving to Atlantic City to accommodate an increasing number of exhibitors as well as an expanding number of Test WeekTM activities for conference attendees, such as panel sessions, tutorials, workshops etc. ITC organizers also want to provide a new venue experience for its attendees.
ITC General Chair Dan Graham, inTEST Corp., says, "The Washington area served us well for a number of years but ITC is growing and we need considerably more space for exhibits and technical sessions. We also believe that a variety of conference sites will be appealing and stimulating for our attendees, so we're taking an inventory of different sites that can meet our needs over the coming years."
The ITC Steering Committee has embarked on a long-term plan to move the conference every few years and will announce future sites as soon as contracts are finalized.
ITC Test Week 1998 will take place October 18 - 23 in Washington, DC, at the Marriott Wardman Park Hotel (formerly the Sheraton Washington Hotel).
Amy Gold, ITC Marketing Chair
Recommendations Solicited
Each year, TTTC recognizes members for their outstanding service by presenting service awards through the Award Program of the IEEE Computer Society. These service awards, which are presented during TTTC-sponsored events, but principally during the Awards Banquet of ITC Test WeekTM, generally fall in one of the four following categories:
Certificate of Appreciation: for creditable service to any TTTC activity or program.
Meritorious Service Award: for meritorious and significant service to any TTTC activity or program (qualification is enhanced by the level and number of contributions, excellence, dedication and tenure of service).
Distinguished Service Award: for long and distinguished service to the TTTC at a level of dedication and achievement rarely demonstrated.
Outstanding Contribution Certificate: for an achievement of major value and significance to TTTC (the achievement should be a specific, concisely characterized accomplishment, as opposed to a collection of different efforts).
If you know someone who should be recognized during the next ITC Test Week (October 18-23, 1998), or if you would like to learn more about TTTC awards, please contact the TTTC Awards Chair, Christian Landrault, tel: (+33) 67-41-85-24, fax: (+33) 67-41-85-00, e-mail: landraul@lirmm.fr).
Christian Landrault, TTTC Awards Chair
Dr. James Beausang, an active and dedicated volunteer in the test community, died on May 21, 1998. James was a mentor and teacher, led by example and helped to develop outstanding engineers in EDA test technology. He was Research and Development Manager for Test Compiler Products at Synopsys, Inc. in Mountain View, California.
James was widely known in the test community where he held numerous professional volunteer positions, including: Chairman of the TTTC Web Initiatives Project; member of the Program Committees of ITC, ITSW and ETW; Panels Chairman of the TECS Workshop; reviewer for several technical meetings, and member of the IEEE P1500 Working Group.
Born in Ireland on September 21, 1962, one of eight children of Tom and Ita Beausang, James was the oldest brother in a close-knit family. From childhood, James applied focus, organization and intensity to every aspect of his life. He had a deep social conscience and demonstrated his compassion for others in many ways. Throughout his life he displayed a strong commitment to family and friends. He excelled in math, music, English and woodwork and played football. James played the violin, performing as a soloist with the University College Dublin Orchestra.
In 1982, after completing his B.E. in Electronic Engineering with First Class Honors at University College Dublin, James journeyed to the University of Rochester, NY USA where he undertook graduate studies with Prof. Alex Albicki. His five years at Rochester culminated with his thesis on Test Control for Self-Testable VLSI Chips. James then joined AT&T Bell Labs, Princeton, NJ. In 1994, James moved to Mountain View, California, to join the Synopsys EDA test team.
Over the years, James made many contributions to test technology. At AT&T, he contributed to the development of the IEEE 1149.1 Boundary Scan Standard and developed boundary scan products. At Synopsys, he helped develop one-pass scan synthesis, hierarchical scan architecture techniques and boundary scan compliance checking.
Colleagues also recognize that James was a consummate software engineer. A scholar of software design, he constantly strove for consistency, quality and robustness in his software and algorithmic designs. He also focused on use models that would allow designers to work intuitively and efficiently with the EDA tools developed by his team.
TTTC Chair Yervant Zorian recently announced that TTTC is developing a proposal for a James Beausang TTTC Memorial Award. The award will be presented to students doing high quality research in Design for Testability. Zorian expects to E-mail a final award proposal to TTTC members by mid-August, and to officially solicit financial support at that time.
A special observance at International Test Conference 1998 in October will honor the memory of James Beausang.
Ken Wagner and Yervant Zorian
HLDVT '98: Design validation and test for designs using high-level specifications
The Third IEEE International High-Level Design Validation and Test Workshop (HLDVT '98) will be held November 12 - 14, 1998 at the Sheraton Grande Torrey Pines in the San Diego, CA, USA area.
The HLDVT workshop aims to stimulate research in test and validation methodologies for ICs and systems specified using high-level descriptions, where high level refers to register-transfer, behavioral, and system level specifications.
For more information, please contact
Sujit Dey, General Chair, e-mail: dey@ece.ucsd.edu
Alex Orailoglu, Program Chair, e-mail: alex@cs.ucsd.edu.
URL: http://www-cse.ucsd.edu/groups/hldvt
Raj Raina, HLDVT '98 Committee
FTCS-29, the 29th International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, USA, June 15-18, 1999, has issued a Call for Papers. Submit a 1-page abstract by Nov. 6, 1998 and eight copies of regular papers by Dec. 4, 1998. For further information on submission of papers, reports on practical experience, demonstration proposals, panel proposals and tutorial proposals, see http://www.crhc.uiuc.edu/FTCS-29/. For additional information, contact the conference General Chair Kewal Saluja,
e-mail: saluja@pascal.ece.wisc.edu
or the Program Co-chair William Sanders,
e-mail: ftcs-29@crhc.uiuc.edu
THERMINIC 98 at Cannes in Fall
The 4th THERMINIC Workshop will be held in Cannes, France, September 27-29. THERMINIC Workshops are a series of events to discuss the essential thermal questions of microelectronics and microstructures. These questions are becoming more and more crucial with the increasing element density of deep-submicron integrated circuits. Dimensional downscaling necessitates thermal simulation, monitoring and cooling. The high element density of MCMs and the mobile parts of some microsystems raise new and unique thermal problems, barriers that must be overcome if the promises of continued downscaling are to be fully realized. On the other hand, these same thermal effects can be used as the bases of sensors or other functional structures.
The 4th THERMINIC Workshop is co-sponsored by TTTC. Previous THERMINIC Workshops were held in Grenoble, Budapest, and Cannes in 1995, 1996 and 1997.
This year, the workshop program includes 22 papers for oral presentation and 24 papers for poster presentation. The oral presentations have been organized in 5 sessions:
1: Dynamic Thermal Measurement and Evaluation
2: Sensors and Actuators
3: Electro-Thermal Simulation
4: Thermal Simulation
5: Thermal Measurement Techniques
In addition, there will be a panel that will address the following issue: "Industry Need for an Integrated Thermal Analysis/CAD Environment: from Chip to Package to System". B. Guenin from Amkor Electronics will chair the panel.
Two prominent speakers will present invited talks: B. Guenin, Amkor Electronics Inc., Chandler, AZ, USA, will discuss Characterization of a Delaminated Interface in a Plastic Semiconductor Package and its Effect on Thermal Performance; R. Mahajan, Intel Corp., Hillsboro, OR, USA, will present Thermal Integration Challenges in Computing: The Need for Predictive Capabilities.
Bernard Courtois
Multi-Chip Module Test Workshop to reconvene in Napa
The fifth Multi-Chip Module Test Advanced Technology Workshop will be held in the Embassy Suite Hotel, Napa, California, September 20-23, 1998. This workshop provides an international forum for practitioners and researchers to discuss current practices and the latest trends in testing MCMs. The program this year will give MCM designers, test engineers, and researchers an excellent opportunity to obtain an in-depth view of the latest MCM test solutions and design- for-test techniques.
Because the complexity associated with test and diagnosis continues to be a critical issue in manufacturing MCMs, we have created workshop sessions to cover typical applications and issues in MCM test, MCM test equipment, strategies for module-level, substrate-level and interconnect test. In addition, there will be a panel session on the challenges faced when going from prototype to high-volume testing.
For Advance Program or general information contact the General Chair Yervant Zorian, at zorian@logicvision.com. The MCM Test Workshop is jointly sponsored by IMAPS, the International Microelectronic And Packaging Society, and TTTC.
You are invited to actively participate in this dynamic workshop, to share with and learn from the best expert practitioners from industry and academia.
Yervant Zorian, LogicVision
National Science Foundation Workshop Studies Test Research Directions
A two-day meeting, sponsored by National Science Foundation, was held in Santa Barbara, California on May 12 and 13, 1998 to discuss academic research topics and education issues in the testing of electronic circuits and systems. The goals of the meeting were to identify emerging and mature research areas within VLSI testing, to address issues related to increasing the impact of the VLSI test field on education, and to identify models and mechanisms for enhancing interaction, collaboration and data-sharing between industry and academia.
Twenty-one academic and industrial researchers participated in the two-day meeting. They formed into four working groups: two focused on the identification of emerging and mature research topics, one targeted industry and university interaction and collaboration, while the remaining group concentrated on test education. The findings and recommendations from these four working groups were documented in a report of the workshop, which is available at http://yellowstone.ece.ucsb.edu/NSF_WORKSHOP.
In order to facilitate focused discussion at the meeting, the meeting organizers conducted a survey prior to the meeting. The survey, which requested responses to 8 questions regarding test research topics, education, and interaction between academia and industry, was sent to about 50 test researchers. More than 40 responses were received. A summary, including survey responses and a list of participants, is included in the workshop report.
The workshop classified testing research into two categories: emerging areas, defined as new and challenging areas where innovative solutions are needed; and mature areas, i.e. those areas that have received extensive attention in the testing literature. The areas that the workshop identified as emerging and mature are listed in the workshop report. The classifications were based on the premise that the goals of academic research are: (1) to provide algorithmic and methodological solutions, as opposed to production-ready tools, (2) to push the frontiers of knowledge, and (3) to produce results that impact industry practices. If these goals are met, high-quality training of graduate students will follow as a by-product.
The workshop also pointed out that certain characteristics or attributes of research topics, when present, may cause a sub-area to be classified as emerging or mature.
The workshop found that research that involves circuits described at RTL or higher levels of abstraction is emerging, whereas research on gate-level circuits, either combinational or sequential, is mature. However, sequential circuit research is encouraged due to the fact that complete solutions are not available, and because of its applicability to other disciplines, such as verification. Other attributes of emerging areas include non-classical fault models, high-performance circuits, timing and delay issues, and core-based designs. Research for techniques to manage complexity, such as partitioning, test reuse, hierarchy, and parallel processing is also encouraged.
On University/Industry collaboration, the workshop found that the interaction between academics and industry is, in general, healthy. However it can be further improved by facilitating a number of initiatives to enhance the exchange of technical information between industry and academia. The workshop recommended a list of possible initiatives, which are outlined in the report. Meeting participants also agreed that, in general, NSF should focus on sponsoring the generation of new knowledge with potential, but longer term, applications. However, it is also recommended that the NSF should consider sponsoring some university proposals with tangible industrial involvement. Contributions from industry would not have to be limited to funding, but could also include funding, designs, data, access to equipment or in-kind engineering resources.
On the education front, the workshop advocated the incorporation of test topics, laboratories, etc. into existing design courses as preferable to creating a new test course. It is also recommended that test courses need to emphasize the context in which test is used, e.g. design, manufacturing, reliability. That is, test should not be taught as a stand-alone topic. The workshop also found that there is a strong need for design textbooks with test topics in them. The test community needs to help the authors of design textbooks to enhance the textbooks with test topics.
More about the workshop is available at:
http://yellowstone.ece.ucsb.edu/NSF_WORKSHOP
Kwang-Ting (Tim) Cheng
IEEE International Workshop on System Test and Diagnosis held in Virginia after five-year hiatus
The 2nd International Workshop on System Test and Diagnosis was held in Alexandria, Virginia, in April 1998. The first such workshop was held in Freiburg, Germany six years earlier. In the current workshop nearly 50 experts from around the world struggled over issues concerning the subject. These experts interacted in many ways throughout the week, including posters, formal presentations, tutorials, panels, and social events.
System level testing, driven primarily by the incessant march of complexity, but also by advances in technology, is increasing in importance. Greater complexity is forcing us to renew our thinking on the processes and procedures that we apply to test and diagnosis of systems. In fact, the complexity defines the system itself, which, for our purposes, is "any aggregation of related elements that together form an entity of sufficient complexity for which it is impractical to treat all of the elements at the lowest level of detail." System approaches embody the partitioning of problems into smaller inter-related subsystems that will be solved together. Thus, words like hierarchical, dependence, inference, model, and partitioning are frequent throughout this workshop. Each of the participants dealt with the complexity issue in a similar fashion, but the real value in a workshop such as this is in the interactions of the participants at a number of events. The interactions tend to highlight subtle differences in approach, leading to synthesized approaches that allow even more progress.
Operationally the workshop developed over two-and-a-half days with five paper sessions, two panel sessions, a rollicking poster session, and a tutorial on the IEEE 1149.5 System Test Standard given by Mr. Harry Hulvershorn, the current chair of the 1149.5 committee.
A number of organizations provided support to the workshop, including the Institute for Defense Analysis who provided the meeting facilities and helped secure a reasonable room rate at the nearby Raddison Hotel. Two social events punctuated the meeting: a cocktail hour provided by Analogy Corp., and a workshop social with lots of food and libations. A digest of papers was provided by the Executive Agent for Automatic Test Systems (PMA-260D). The most interesting aspect of workshop production was that the Call-for-Papers, paper submittals and registrations were all done electronically, with actual payment at the door. The workshop fee was only $75.00 for IEEE members ($150 for non-members), proving that workshops don't have to be expensive.
The next System Test workshop is in the planning phases. The organizers anticipate holding it in conjunction with ITC '99 in Atlantic City. If you have ideas for sessions or elements of the workshop, please contact Randy Simpson, rsimpson@ida.org or John Sheppard, jsheppar@arinc.com.
The IEEE International Workshop on System Test and Diagnosis is sponsored by TTTC.
Article by William R. Simpson
Southwest Test Workshop sets another attendance record
The 1998 Southwest Test Workshop was held at the Princess Resort Hotel (renamed the Paradise Point Hotel during SWTW) in San Diego from May 31 to June 3, 1998. This was the fifth year the workshop focused on microelectronic wafer-level testing. 416 wafer test professionals registered, a new record attendance for SWTW, surprising in light of the severe travel restrictions in place at numerous semiconductor companies
The workshop began on Sunday afternoon with special activities for early arrivals. Some enjoyed an excursion to the nearby Torrey Pines Hang Glider port where photogenic gliders and parasails soared over the Pacific on a beautiful afternoon. We were all surprised to discover that the glider port was just north of San Diego's famous, bathing-suit-optional, Black's Beach. Out came the telephoto lenses! Meanwhile, 175 earlybirds attended the first SWTW Probe Technology Tutorial. Three presentations were given on the topics: gauge R&R, probe card manufacturing and metrology. In addition, a description of the SEMI task force Probe Standard recently sent out to ballot was presented.
The workshop officially began at 5:00 pm Sunday with registration, a get acquainted reception, and a Mexican buffet dinner. This year, the traditional Sunday evening panel session took on a unique challenge. Although SWTW has always tried to inform equipment and service suppliers about the needs and expectations of semiconductor manufacturers, we had never before specifically and formally addressed this task. Therefore, six panel members from semiconductor manufacturing companies described in detail what they want and expect, today and in the future, and listed their priorities in terms of price, performance and other factors. Their opening statements were followed by an active audience discussion.
The technical sessions began Monday morning with a contact resistance session starting with a presentation on the theoretical aspects and followed by two presentations on the extensive empirical data taken for a Sematech study. The next session focused on two brand-new probe card technologies and unique recent advances in probe needles. After lunch, we held a session on probe needle cleaning including in-situ methods on probers, unusual tricks and lessons learned, and an excellent survey of five different cleaning methods (which ended up winning the best presentation award).
Following the afternoon break were three non-overlapping parallel breakout sessions. The first session, in the specialized area of RF probing, had three presentations that discussed RF characteristics of materials used in probe test fixturing, new RF software simulation and modeling tools, and characterization of some membrane probe cards. The second parallel session featured a panel and audience discussion of reducing the cost of wafer testing. Discussion topics included baselining, where costs could be reduced by improved equipment utilization, sample probing, reduced test times, and many others. One important point that came up was that wafer test cost is sometimes actually increased to achieve reductions in back-end test cost; the real goal is to reduce overall product cost. The third session also featured a panel and attendee discussion. It concentrated on the somewhat unique technologies of memory probing including massively parallel probing, offline redundancy repair, BIST, and full wafer burn-in.
After a hard day of probe technology, the attendees enjoyed a cocktail party at the hotel's Barefoot Bar, and then a great dinner in the Sunset Ballroom overlooking Mission Bay. After dinner, everyone was invited to continue informal technical discussions, have a little more dessert, and enjoy some after-dinner "cordials" in another conference area.
Tuesday morning began with a session on overall probing accuracy. Four presentations discussed the effects of docking, prober accuracies, and temperature on the ability to hit within a few microns of the center of probe pads - every pad, every time. The next session focused on area array probing, where the probe pads are distributed over the entire area of the die instead of being restricted to the perimeter. The first presentation was an overview from Sematech describing interesting technology drivers, present and future trends, and some informative cost benchmarks. The next presentation was an excellent summary of the over 20 years experience at IBM: this was followed by another presentation on the cost issues of vertical probe cards.
Tuesday afternoon was dedicated to social interaction. Since more than 50% of the value of a workshop is in the informal technical discussions, SWTW does not simply encourage them; we make them happen. Three activities were available: thirty-seven people played miniature golf at the hotel course and a few more opted for a higher level of play at a nearby Torrey Pines course; 250 attendees and spouses spent the afternoon at Sea World; and about 125 boarded a misplaced Mississippi Stern Wheeler at the hotel dock for a two-hour sightseeing cruise around Mission Bay. Official SWTW hats and suntan lotion were passed out to all.
Tuesday evening we enjoyed another cocktail party and then our awards banquet. Awards were given for the best data presented, best overall presentation, lowest miniature golf score, and poorest disguised sales pitch (The Royal Order of the Golden Wheelbarrow full of Crap). It is somewhat unusual to have an awards banquet before the workshop is completely over, so the SWTW also gives an award to all the last day presenters from last year. The coveted SWTW Worst Sunburn Award could not be given because the official SWTW suntan lotion was only SPF4 due to a shipping error, resulting in too many qualified recipients.
Our first session Wednesday morning concerned fine-pitch probe cards. With higher I/Os and device shrinks, tighter pitch perimeter cards are becoming more important. The session had three presentations on cards with pitches of 67, 45, and 40 micrometers. The final session was on the various issues of wafer testing in order to supply Known-Good Die. The first presentation was an overview of KGD including the activities of a Die Products Consortium of major manufacturers. This was followed by a presentation on full wafer burn-in, and then a presentation of the EIA/JEDEC JC-13 KGD standard. The final presentation described the successful approach for testing a complex 1500 I/O device requiring over 70 watts, appropriately entitled, "Scotty, I need more power!"
By most measures the 1998 SWTW was the best yet. We tried some new things such as the Probe Tutorial, and we increased the activities for informal discussions. We had three excellent panel and audience discussions and 29 technical presentations. A copy of the presentations will be posted on the Computer Society web site, a CD ROM is being made for attendees (in addition to the printed conference proceedings handed out during the workshop). We plan to give copies of the CD ROM to attendees of the special probe session planned for the 1998 ITC. The next SWTW will begin Sunday afternoon, June 6, 1999 at the Paradise Point Resort in San Diego.
Bill Mann, SWTW Chair
4th IEEE Mixed-Signal Testing Workshop 1998 in The Hague
>From June 8th until June 11th, the 4th IEEE Mixed-Signal Testing Workshop (IMSTW) was held in The Hague, The Netherlands. The workshop was attended by 82 people from 16 countries, showing a continued interest in mixed-signal testing issues. In total, 53 contributions were presented either in presentation or poster form. Topics included fault modeling, simulation, IFA and test generation. Also DfT issues such as current-testing techniques and BIST, were extensively discussed. Sessions on virtual testing and industrial experience also evidenced growing interest. A lively panel session debated the future of specification tests in respect to the growing application of defect-oriented testing.
New were two "live" demo sessions from companies and academic institutions in the area of test tools and (remotely-operated) simulators in front of the whole audience.
The 300-page informal proceedings shows a large industrial and academic effort in the topic of mixed-signal testing in both Europe and North-America.
The next IMSTW meeting will be held in Vancouver, B.C., Canada.
2nd SPI Workshop: a "great success" in Germany
The 2nd IEEE Workshop on Signal Propagation on Interconnects was held in Travemuende, Germany, from May 13-15, 1998. Eighty-three experts working in this field - a third from universities and from various countries (USA, France, Netherlands, Canada, Sweden, Switzerland, Poland, Italy, Singapore, Belgium and Germany) met in a relaxing atmosphere in the Kurhaus-Hotel to discuss and to share their latest research results and developments.
During the two-and-a-half days, 29 papers and 10 posters were presented. The contributions covered a wide area, dealing with topics such as: ground bounce effects, substrate influences on signal propagation, simulation, measurement and modeling of interconnect structures, parameter extraction, numerical methods, and new trends in high-speed interconnects.
As was done after last year's workshop, a selection of representative contributions will be published in a book from Kluwer Academic Publishers, Dorderecht and New York.
Workshop participants enjoyed a cruise in the Luebecker Bucht and down the Trave. A typical "Waterkant" buffet was served while cruising. Among other sights, we had the opportunity to see the old windjammer "Passat", a sailing ship of 115m length with four masts and square sails.
All in all, the 2nd SPI Workshop was a great success. We plan to hold the next SPI Workshop in the southern part of Germany, May 18-21, 1999. We will be happy to welcome you to SPI'99.
Information about the past workshops as well as on the one to come can be found at:
http://www.tet.uni-hannover.de/SPI/spi.htm.
Petra Nordholz
Paris hosts 1st DATE Conference
The DATE'98 conference in Paris took place February 23-26 as the first co-ordinated, unified and single main European event in Design Automation and Test of Electronic-based systems. DATE'98 was a very big success in quality and in numbers and has set an opening chord for what promises to become a very interesting, entertaining and successful series of conferences.
The term 'European' only refers to the location of the conference. In all other respects, DATE is a truly international event with strong participation from the United States and Japan, among many other non-European nations. The international participation in paper presentation as follows:
Submitted Accepted
Germany 22% 28%
USA 21% 27%
France 9% 5%
Spain 7% 7%
Australia 5% 4%
Italy 5% 6%
Netherlands 4% 5%
Rest of Europe 20% 15%
Rest of World 7% 3%
The paper sessions ran in four major tracks, a balance between the main topics of the conference: design, automation and test.
Besides papers, the conference provided for 'hot topic presentations by advanced topic developers and panel discussions featuring selected "heavyweights" in their respective fields. The hot topics were: IP-Based System-on-a-chip Design, Reconfigurable Systems, Silicon Debug of Systems-on-a-Chip, and Embedded Memory and Logic.
The panels covered the topic of Formal Verification in an Industrial Design Flow and Next Generation Design Tools.
The opening session of DATE'98 was devoted to a number of topics. First, we provided a retrospective of DATE's recent eventful history, a review of the program; and a forecast for the future. The main opening session features were presentations by three eminent personalities in our community. Theo Claasen, Chief Technological Officer of Philips Semiconductors, made a very convincing case for a paradigm shift in chip design to 'systems-on-a-chip.'. Rajeev Jain, UCLA, provided a glimpse of what it means to think 'mobile and wireless telecommunications' all the way down to the circuit level, and how obsolete the old area-time trade-off has become in favor of a power-throughput trade-off, among others. Electrical engineering has not become less important, quite the contrary! The last main speaker was Yervant Zorian who concentrated on 'embedded quality assurance', the logical successor of BIST. As chips become more intelligent, part of that intelligence is their self-testing and even self-repairing abilities. At the close of the opening ceremony, the paper awards of ED&TC'97 were presented: in the CAD category to: W. Verhaegh, P. Lippens, E. Aarts and J. Van Meerbergen for the paper Multidimensional Periodic Scheduling: A Solution Approach, and in the Test category to: W. Sachdev for the paper Deep Submicron IDDQ testing: Issues and Solutions. The ceremony found its apotheosis in the Award of the IEEE Computer Society to Gordon Adshead for his relentless efforts to building a conference in the design and test area, culminating in DATE.
The commercial exhibition at DATE'98 was also a great success. Not only because of the numerous, very attractive and informative booth displays, but also because of the vendor presentations and hands-on sessions. The tally of visitors to the exhibition was close to 4,000, the number of participants in the technical program was 767. In view of this very pronounced success, we believe that DATE is indeed marked for some further increase in the future. However, we do not aim at sheer large numbers but at consistent quality both in the technical program and in the exhibition. A good balance between the two types of activities is very important to us. We believe that the conjunction of a technical conference and a commercial exhibit is a very good thing, provided each one is of the highest possible quality.
DATE'99 will be held in Munich, March 10-12. The General Chairperson will be Rolf Ernst of Braunschweig University of Technology. Dominique Borrione of TIMA, Grenoble will occupy the Program Chair. Information on DATE'99 can be obtained at the website: DATE99@imag.fr. The new conference committee team will without doubt improve on what has been achieved so far. Topic-wise and format-wise there will be no major changes from DATE'99, but the details will change. We shall be taking suggestions for improvement to heart.
P. Dewilde, DATE'98 Conference Chairman
Germany hosts Systems Test Workshop - TWS '98
The 10th Workshop on Test Methods and Reliability of Circuits and Systems, organized by a joint working group of the German organizations GI, GMM and ITG and by TTTC, was held in Herrenberg near Stuttgart, Germany. Over 60 attendees, more than half of them from industry, took part in a very interesting workshop with lively discussions. In the keynote address, Bernd Koenemann, vice president of LogicVision in San Jose, California and a pioneer in the design of self-testable circuits, gave an informative and current overview about the test problems of Systems-on-a-Chip. These systems consist of very different modules, analog parts, memory arrays and pre-designed embedded cores. The testing of such a system makes great demands on external test systems, leading to significant costs. Today the market for test equipment of microelectronic systems is large, larger than the market for electronic design automation tools. Due to both technological and economic reasons, this trend cannot continue on this scale so an increasing portion of the test function will be integrated into the chip.
In addition to the keynote session, the workshop featured five technical sessions on the topics of reliability, design for testability, BIST, on-line test, test concepts for controllers, fault modeling and fault simulation.
Stuttgart is the home of both Mercedes-Benz and Porsche, so the testing of automotive electronics received special attention. T. Thurner, Daimler Benz, explained the so-called "X-by-wire" concept, where a main car function is controlled electronically. For example, a joystick not unlike one used to play a computer game may replace a vehicle's steering wheel. The implications on reliability and fault tolerance of X-by-wire were extensively, sometimes controversially, discussed.
Especially interesting for students and graduate students was the evening panel where representatives from Bosch, Hewlett-Packard, IBM, Philips and Siemens discussed the knowledge and skills needed by a technical employee in the area of test and reliability of circuits and systems. It turned out that the specific requirements are absolutely different depending on the particular application. But everyone on the panel agreed that these employees need a very broad knowledge in both electrical engineering and software technology. However, the ability to design and encode software is taken for granted, whereas in-depth knowledge about the technology and hardware actually gives a competitive edge to a prospective employee.
Prof. Dr. Hans-Joachim Wunderlich, University of Stuttgart chaired TWS '98. His university division of computer architecture organized the event.
Hans-Joachim Wunderlich, TWS'98 Chair
VLSI Design and Test Workshops: August 6-7 in New Delhi, India
For the second time, the VLSI Design and Test Workshops are being held in India. Since the first set of VDT workshops were held during the International Conference on VLSI Design in January 1998, were so well attended and successful, most participants felt that a similar event should be held without waiting a full year. Therefore, a second set of VDT workshops were organized and scheduled for New Delhi, India on August 6-7, 1998. The VLSI Society of India, TTTC, and the Computer Society's VLSI TC are sponsoring the event and several industries in India are providing support.
The scope of the workshops is to promote applications and research related to all aspects of VLSI. The program consists of three simultaneous workshops: Test Workshop, Logic Design Workshop, and Physical Design Workshop, organized as three parallel tracks of six sessions each. Vishwani Agrawal, Lucent Technologies Bell Laboratories, provided overall guidance for the organization of the event, while C. P. Ravikumar, Anshul Kumar, and B. Bhattacharya were the Program Chairs for the three workshops, respectively. Dr. Ravikumar and Prof. Anshul are with IIT Delhi, and Dr. Bhattacharya is with ISI Calcutta. The workshop features thirty-two paper presentations, three invited tutorials, an invited talk by an industry expert, and a panel session on VLSI design and test education.
The workshops venue is The Habitat World which is located on Lodi Road, New Delhi. The workshops' Web page at http://iitd.ernet.in/menu/Conf.html can be consulted for more information.
Brazil and Argentina to cooperate in HW-SW Co-design Project
Project has an open research position
This September, Professors Fabian Vargas, of the Catholic University, Brazil, and Maria Schiavon, of the National University of Rosario, Argentina, are initiating a cooperative project in the field of hardware-software co-design of on-line testable systems for critical applications. The governments of both nations will support the project and the Brazilian Institute for Space Research (INPE) is cooperating with it. The project goal is to develop a design environment and general rules for an automated hardware-software co-design process for electronic systems with extensive use of on-line fault-detection. The resulting CAD environment will also support a reliability verification tool to ensure the conformity of the system with specific applications.
The project has an employment opening for an associate professor under a research grant from the Brazilian Government. The position, which is in the Electrical Engineering Dept. of the Catholic University of Brazil, is for a 24-month period (perhaps renewable for another 24-mos.). Candidates should have knowledge of at least: computer architecture, HW-SW partitioning and co-simulation techniques, testing-related approaches for on-line fault-detection and/or correction, reliability estimation issues, SW testing, and system reconfigurability.
For more information about this position, send e-mail to Prof. Fabian Vargas, vargas@ee.pucrs.br
Fabian Vargas, TTTC Group Chair, Latin America
The Y2K Millennium Problem: More Solutions, Testing, Triage, and Certification Information
When you read this, there will be only about 500 days before the Y2K millenium problem may seriously impair computer systems that affect you, unless the people responsible for those systems have fixed them. Recent articles in major media such as Time, and Business Week have highlighted what could happen to the nations power networks, air traffic control system, banking and financial systems and more. It also could affect your test system and your personal computer. What are your company's Y2K contingency plans?
Here is a continuing report on the status, the testing issues, certification issues, and the latest solutions of the Y2K Millennium Problem.
Y2K is the largest and most important test issue to face the US and the rest of the industrialized countries of the world in this century. Even Microsoft has finally acknowledged the possibility of Y2K issues in their application software, (it was recently reported that their flagship NT operating system needs a patch to become Y2K compliant), and has opened a new www page at www.microsoft.com/year2000 to address them.
As we approach 2000, it becomes more and more difficult to complete all the Y2K fixes needed before the millennial deadline. Many companies are already forced by a lack of time and manpower to consider "triage" solutions, where they search for and fix only those systems which absolutely can't be permitted to fail while allowing systems of lesser importance to go unchecked and to fail if they will.
For some companies the deadline to get this problem fixed has already passed. For example, financial companies dealing in securities had to fix the problem by a June 15, 1998 deadline or risk formal warnings from federal auditors, a situation that could have caused their stock values to fall. Worse, these companies have just one year from the time they are found non-compliant. If they are still not compliant, they risk being shut down! In another financial example that everyone can relate to, many people have had their new credit cards refused because of an expiration date after 2000.
Many companies think the new PCs with Pentium CPUs that they bought in 1997 are automatically Y2K compliant. This may not be true depending on the date of the BIOS Chips inside their computers, the type of operating system they use (both Microsoft Windows 95 and NT 4.0 require Y2K patches), and the applications they run.
The year 2000 problem will affect all modern industrial countries on every continent in major ways. But many European corporations are still denying to themselves that a problem exists. Some experts suggest that corporations that do regular business internationally should start now to dialog with their foreign clients or suppliers on Y2K issues. Ironically, Russia and other former soviet block countries might be affected to a much lesser degree since they do not depend on computers as heavily as the west does.
The Y2K Problem goes well beyond "00"
1. In computer software/firmware from as recently as the mid-80s, the year is coded using only two digits so that in the year 2000, the two-digit field will role over from 99 to 00. Many computers (mainframes, client/servers, workstations, PCs, MACs, CPUs, DSPs, state machines, etc.) if they continue to work at all, will recognize this as the year 1900.
2. Many older application programs use 98, 99, and 00 as reserved fields that mean specific things, like end-of-sequence.
3. Programs that calculate dates generally recognize leap years and add in an extra day for February 29. But century years are not leap years unless divisible by 400. 1900 was not a leap year, but 2000 is a leap year.
4. There could also be a time zone problem. Computers in different time zones will get to the year 2000 at different hours, possibly causing problems in networks when they interact.
5. Roll-over registers that store date data could be a problem. On August 22-23, 1999, the Global Positioning System (GPS) Satellites will experience this rollover and may fail at that time.
Y2K Solutions
Some companies will shut down their computer systems on Jan. 1, 2000, a Saturday, as a fail-safe measure. Other companies are considering replacing older PCs with new letter-certified PCs at a cost of $1,500, or more, each.
All software that must work across the millennium date should be examined and Y2K certified. Experts recommend that companies get their computers, LANs, DSPs, and related application software and firmware, "letter certified" (i.e. in writing) from their vendors. If this is not possible, they at least need noncompliance work-around contracts specifying compliant replacement parts, etc. Once compliance has been certified, it is up to individual companies to test the compliant products to ensure that the specific implementation of the products are still compliant.
Remember it is possible to use a compliant product in a non-compliant way. This is why a whole system must be tested. Tests may have to include subcontractors and vendors!
Even with vendor-developed Y2K software tools, fixing a Y2K problem is not a glamorous job. It is very tedious even for a team of engineers or programmers to check the enormous number of lines of source code, sometimes handwritten, for thousands of different applications. The chance of introducing new errors while fixing a Y2K problem in older programs with hundreds of thousands of lines of code is very high.
The USAF has implemented a five-step plan to address Y2K problems. The steps are:
1. Awareness - Make all players aware of the problems in all affected programs.
2. Assessment - Determine Y2K impacts to your systems, to those you interface with and formulate a plan to fix, correct, test, migrate or decommission the systems.
3. Renovation - Modify systems to be Y2K compliant.
4. Validation - Test and verify that systems are compliant, then certify it in writing.
5. Implementation - Deliver corrected systems.
A free nine-page USAF Y2K certification form is available at the USAF web site at http://year2000.af.mil
Y2K solutions are not difficult
The "hard part" is systematically analyzing the problem in your company, checking to see if your vendors and contractors are using the same solutions, and then convincing top managers of the situation. The most difficult part is to have them devote enough money and personnel to fix it.
Y2K References
There are two good recent books on the subject of Y2K. Managing 00, Surviving the Year 2000 Computing Crisis by P. de Jager and R. Bergeon, John Wiley & Sons, 1997, is good reading. Another excellent reference, The Year 2000 Software Problems, by Capers Jones (www.spr.com), Addison-Wesley Longman, Inc., 1998, contains specific steps to take if one is starting Y2K software repairs in 1998. It lists over 400 software languages affected by the Y2K problem as well as companies and consultants for Y2K solutions, and a comprehensive glossary of terms.
For a great outline of the Y2K problem and some solutions, reference Info World, Volume 20, Issue 19, May 11,1998. pp 82-86, 103-107. Computerworld, March 9, 1998, has two great articles on Y2K compliance of corporation suppliers, p28 and p76.
WWW sites for Y2K news:
www.2k-times.com/y2k.htm (latest
articles on Y2K)
www.year2000.com
www.digital.com/info/year2000
www.mitre.org/research/y2k
www.army.mil/army-y2k/
This article is based on material first published in two issues of the newsletter of the American Society of Test Engineers. See www.astetest.org
Michael E. Keller, TTTC Associate Editor, Dynamics Research Corporation. e-mail: astetest@aol.org
This newsletter is the informal publication of the IEEE Computer Society Test Technology Technical Committee. We will publish all appropriate material although editing may be necessary to meet space or typographical constraints. Articles are not refereed unless so noted. Opinions are those of the contributors and are not necessarily the opinions or positions of TTTC, the IEEE, or the IEEE Computer Society.
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