_________________________________________________________________

Test Technology Newsletter

May -- June, 1997

The Newsletter of the Test Technology Technical Committee of the IEEE Computer Society

_________________________________________________________________

Still growing:

ITC Test Week adds another workshop

Early this November, International Test Conference, long recognized as the premier event in electronic test, will host three specialized test workshops:

- Testing Embedded Core-based Systems Workshop

- International Workshop on the Economics of Design, Test and Manufacturing

- International Workshop on IDDQ Testing

The three workshops will be the last events of n ITC'97 Test Week , five full days of informative, educational and social events dedicated to electronic test. Test Week will commence with tutorials on Saturday, November 1 and continue until the workshops close the week on Thursday, November 6. Most of the Test Week events will be held at the Sheraton Washington Hotel in Washington, DC, USA.

The 1997 ITC will be the first one to host three workshops. Holding workshops in conjunction with ITC began in 1995 when the first IDDQ Workshop was held there. It's success demonstrated the benefits of holding a specialized workshop in conjunction with the industry's premier event. In 1996, organizers of the established plain Economics Workshop, which earlier had been held in Texas, moved it to the ITC venue. This year, hoping to emulate the success of those two workshops, the organizers of the new ain Testing Embedded Core-based Systems Workshop (TECS) decided to inaugurate their meeting at ITC.

Embedded cores, or pre-designed Intellectual Property (IP) megacells, are finding growing use in microelectronic systems. Core-based systems benefit from reduced design costs made possible by re-using core designs but are more complex to test. TECS will be the first technical meeting to dedicate its program to emerging trends and new methods of testing embedded core-based systems. TECS will bring together core creators, integrators and manufacturers in an informal forum for presenting and discussing the new developments in testing such systems.

The 5th International Workshop on the Economics of Design, Test and Manufacturing for electronic circuits and systems (EDTM) aims to provide a friendly forum for discussing and exploring current and future design, test and manufacturing trends and how they are driven by the economics of delivering increasingly complex microelectronic systems. The workshop focuses on the dollar impact of the decisions made in the design, manufacturing, test and field maintenance of electronic devices, modules, boards, and systems.

IDDQ testing, a technique used to screen a large portion of the digital ICs manufactured today, also has made significant inroads in analog and mixed-signal testing. The 1997 International Workshop on IDDQ Testing (IDDQ97) will address, in an informal setting, recent advances and research issues related to IDDQ testing, especially the challenges in ensuring high fault coverage in sub-micron ICs.

In addition to the workshops, Test Week will include:

> 16+ test tutorials

> A Plenary Session with key presentations by top industry leaders.

> 100+ exhibits by the leading purveyors of test equipment, software and services.

> 100+ first-rate technical papers on the latest developments in test.

> 8+ panel sessions where test issues are frankly discussed and audience interaction is in order.

> 30+ commercial presentations by the leading purveyors of test products.

> Social events and frequent social breaks to facilitate networking and continued discussion.

> Many meetings of professional committees, user groups, standards groups, etc.

> The three Test Workshops discussed in this article.

All in all, ITC'97 Test Week offers much to every test professional. ITC typically has so many must-see events that most attendees have difficulty scheduling everything they would like to attend. Year-after-year, surveys show that nearly all ITC attendees want to return to future ITCs. With the addition of the newest workshop, ITC, more than ever, is truly the outstanding global event for professionals in electronic test.

International Test Conference is sponsored by the Test Technology Technical Committee of the IEEE Computer Society and the IEEE Philadelphia Section . The tutorials at ITC and the three workshops are sponsored by Test Technology TC.

For more information, contact:

ITC Test Week: ITC Office, tel: (202) 973-8665, e-mail: itc@courtesyassoc.com

TECS: Y. ZORIAN (General Chair), LogicVision, e-mail: zorian@lvision.com

EDTM: Tony AMBLER (General Chair), University of Texas, e-mail: ambler@ece.utexas.edu

IDDQ97: Carol TONG (General Chair), Viewlogic - Sunrise Test, e-mail: ctong@viewlogic.com

___________________________________________________________________________________

New TTTC meeting format to get trial at ITC'97

At the Operations Committee meeting in Monterey on April 28, TTTC Chair Yervant ZORIAN noted that it is becoming more and more difficult to schedule and run well-attended committee meetings. TTTC's vitality and growth have brought about a condition where many TTTC leadership committees, as well as many activity groups and meeting committees, want to hold their meetings at ITC and VTS. What better place to meet than at TTTC's major conference or symposium? There is minimal difficulty in getting company or university support to attend them and they offer a major opportunity to network. The downside is that ITC has gotten so busy that it is impossible to attend everything you should technical papers, panel sessions, committee meetings and VTS is rapidly getting that way. There's only so many hours at these meetings and many things seem to be scheduled at the same time.

Zorian initiated a discussion of what could be done to alleviate the problem insofar as TTTC meetings are concerned. OpCom decided that the TTTC's meetings should be held in a sequence designed to minimize duplicate reporting and to eliminate the need for many volunteers to attend multiple meetings.

The committee recognized that a key to the success of this format is to have more detailed reporting occur in the early meetings and to have TTTC's Group Chairs summarize the activities and recommendations of their groups in the later meetings, culminating in the OpCom meeting.

The committee decided to give the new format a trial run at November's International Test Conference. Zorian, working with the appropriate Group Chairs, and any activity or technical meeting committee chairs who wish to hold meetings at ITC, will work together to develop a schedule for all TTTC meetings at ITC.

Any TTTC volunteer leader who wishes to hold a meeting at ITC '97 should contact the TTTC Office. Call (814) 941-4669 or send e-mail to: EdDor@aol.com.

A schedule of major TTTC meetings at ITC will be published in the September October issue of TTTC Newsletter.

___________________________________________________________________________________

TTTC Newsletter adopts new byline policy

TTTC Newsletter has changed its longstanding policy for bylines. Under the former policy only the name of the contributor of an article was given in the byline. The name of the reporter/writer's employer was not published. Under the new policy, the employer's name will be included whenever requested by the contributor of an article.

The newsletter has omitted contributors' employer affiliations of contributors since its inception. This policy supported TTTC's efforts to raise the professional image of test engineers by affirming that the articles were reported and written by individual professionals whose capabilities and expertise were not dependent on who employed them.

At the behest of one of our frequent contributors, who pointed out that his company gives internal recognition for publishing if the company name appears with the article, TTTC Newsletter decided to examine the policy in light of today's realities. We conducted a survey of OpCom members to determine their experiences and opinions.

A large majority of those who responded to our survey favor publishing the employers name or giving the contributor the option of having the employer's name included. They argued that some employers give credit, even bonuses in a few cases, for published articles and that contributors often use their employer's facilities to write their contributions.

A vocal minority of respondents pointed out that including the employer's name could be interpreted as implying that the employer concurred with the article's contents. Those in favor of the old policy also pointed out that, while it is appropriate to include the employer's name with formal papers that undergo formal reviews, it is not appropriate in informal, unreviewed newsletter articles. Also raised was the question of retaliation, legal or otherwise, against a contributor or even against TTTC if something that an employer didn't like was published. One respondent said he recently had a problem like this with his company. Finally, a respondent pointed out that just the possibility of problems could have a chilling effect on what people would contribute if the employer affiliation were included.

Taking all of these opinions into consideration, we have decided to publish the employer's name so our contributors receive credit from their employer. However, we will include it only when the contributor specifically requests it so that contributors can feel free to express opinions that may not be politically correct at their place of employment.

Contributors who request inclusion of their employer's name will shoulder any responsibility for problems that might arise with their employers. Where there is a possibility of a problem, contributors should state in the article that it is the work of the contributor alone and doesn't express any views of the employer.

TTTC Newsletter thanks Associate Editor Michael Keller for bringing this issue to our attention. We also thank all the OpCom members who expressed their opinions in our survey.

Ed Thomas, Editor

_____________________________________________________________________

Call For Participation:

IEEE International High-Level Design Validation and Test Workshop

Nov. 14-15, 1997

The Claremont Resort & Spa, Oakland, California

The Second IEEE International High Level Design Validation and Test Workshop aims to stimulate research in test and validation methodologies for ICs and systems specified using high-level descriptions, where high-level refers to register-transfer, behavioral, and system-level specifications. The goal of the workshop is to provide an informal forum that brings together designers, test researchers and verification researchers who are working in validating, debugging, and testing designs, in an effort to address high-level design validation and test issues concurrently.

Prospective authors should submit an extended summary of 1000 words describing their original, unpublished recent work. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. On the title page, indicate: title, name and affiliations of all authors, and suggested topics. Identify a contact author and include a complete mailing address, phone number, fax number and e-mail address. Panel proposals are also invited. Submit seven copies of the proposal by mail or a Postscript version via e-mail. Submissions are due no later than August 1, 1997.

The workshop will notify authors of the disposition of their papers by September 15, 1997. Submission of a proposal will be considered evidence that upon acceptance the author(s) will present the paper at the workshop. Authors of accepted papers may submit a full version of their paper by October 15, 1997 for inclusion in an informal digest of papers, which will be distributed only to attendees of the workshop.

The Second International High Level Design Validation and Test Workshop is sponsored by the Test Technology Technical Committee of the IEEE Computer Society and by the Design Automation Technical Committee of the IEEE Computer Society.

Submit all paper proposals to:

Sujit DEY, Program Chair, NEC USA

4 Independence Way, Princeton, NJ 08540

T: 609-951-2973, F: 609-951-2499

e-mail: dey@ccrl.nj.nec.com

For general information, contact:

Prab VARMA, General Chair, Duet Technologies Inc.

2833 Junction Ave., #100, San Jose, CA 95134

T: 408-432-9200, F: 408-432-0907

e-mail: prab@duettech.com

Material submitted by HLDV&T Workshop

___________________________________________________________________________________

Testers: Beware of forgeries of ICs and other parts

Recently a CPU forgery ring was broken up in Central Europe after a year long investigation, according to the German weekly magazine Der Spiegel. Intel 133-MHZ CPU chips were stolen and their markings were altered to 166-MHZ. These chips were then resold to well known computer manufacturers as 166-MHZ CPUs. The forgeries were so good that even Intel experts had trouble telling true parts from the bogus ones.

The bogus CPU chips worked for a period at the higher speed but ran much hotter than their specifications so they tended to fail sooner than true 166-MHZ CPUs. This led to more field failures than expected. This type of bogus part could lead to disastrous results if used in medical or mission-critical applications.

Investigators believe there are many other manufacturers of bogus ICs yet to be caught. According to recent literature, giant CPU-chip makers are fighting back with innovative markings such as holographic microtag images invisible to the naked eye, etc.

The problem extends not only to ICs but to other parts as well. For example, TIME Magazine recently reported (March 31, 1997, pp. 58-59) that over 40% of replaceable parts in military and commercial airplanes are bogus!! This includes simple mechanical parts like fasteners, screws and bolts as well as more complex components such as hydraulic pumps, etc. If bogus replaceable parts are this prevalent in the aircraft industries, it is reasonable to suspect that other industries may also have the problem.

These documented events build a very strong case that components that come from any source other than the original manufacturer need to be thoroughly tested and inspected for authenticity on a piece-by-piece basis before being used in critical system assemblies.

This article is condensed from an article originally published in the American Society of Test Engineers Newsletter 1997 Volume 3.1 and 3.2)

Article by Michael E. Keller, TTTC NL Associate Editor

Dynamics Research Corporation

mkeller@S1.drc.com

___________________________________________________________________________________

Standards in Test: TTTC Standards Activities News

Mukund Modi joins Pat McHugh in coordinating

TTTC Standards Group

Mukund MODI, Naval Air Warfare Center, has accepted the position of TTTC Standards Group Vice Chair, joining Group Chair Pat McHUGH in coordinating the group's activities. TTTC Chair Yervant Zorian who announced Modi's acceptance at the April 29th OpCom meeting, noted that Pat has extensive connections in IEEE standards circles while Mukund has similar experience and connection within TTTC. Together the pair is expected to strengthen TTTC's efforts in standards.

Also at the OpCom meeting, TTTC's role in test standards was restated as: 1. Identify needs for new standards in test and initiate standardization activities; 2. Nurture new standards in test by supporting their early development; and 3. Identify other test standards and communicate them to TTTC members.

_____________________________________________________________________

Standards Activity Summary

A summary of the test standards that are directly supervised and developed by Test Technology TC Standards Group:

IEEE 1149.1EEE Standard Test Access Port and Boundary Scan Architecture

Chairman: C.J. CLARK

Email: CJCLARK@Intellitech.com

This working group has a balloting body that was formed earlier but it is soliciting new members. The WG expects to go to ballot in June 1997 with ballot resolution and approval scheduled for October 1997. The group is currently developing text to clarify some areas that have been questioned. The revision will include the original standard and as well as BSDL. Additional material is planned to detail the use of IEEE 1149.1 with differential signals and to support IEEE 1149.1 with analog I/O. The next project will be the detailing of additional constructs to allow the use of 1149.1 for in-system configuration.

IEEE P1149.4 -Mixed Signal Test

Chairman: Adam CRON

Email: acron@commerce.wes.mot.com

This group is very close to completing their initial draft for balloting. A balloting group is presently being formed. The draft is scheduled to be sent out for ballot in June 1997 with ballot resolution and approval in October 1997. This standard addresses specific needs of mixed-signal ICs by defining a specific architecture and constraints that are necessary in order to use the IEEE 1149.1 standard interface to gain access to an IC for mixed-signal test and measurement.

IEEE 1149.5 - Module Test & Maintenance Bus

Chairman: Harry HULVERSHORN

Email: harryh@lvision.com

This standard group is presently discussing changes to the present standard which will be published in a supplement (Fall 1998). The 1149.5 standard details a protocol and a message layer for the communication of test and maintenance data either in-system or in a maintenance activity. Much of the group's activity is focused on developing a user group and the environment needed to use this interface as an in-system test and maintenance interface.

P1450 -Standard Test Interface Language (STIL) for Digital Test Vector Data

Chairman: Greg MASTON

Email: maston@chdasic.sps.mot.com

This standard group is currently developing a draft detailing of the Standard Test Interface Language. STIL is a language that will support the transportation of digital test vector data from creation to use on automatic test equipment. A draft was scheduled for ballot in May. The group expects that balloting and resolution to be completed this fall.

P1500 -Embedded Core Testing Group

Chairman: Yervant ZORIAN

Email: Zorian@lvision.com

This standard group is developing the techniques and architecture that will simplify the testing of embedded cores that are contained within ASICs. The group is currently discussing scalable architectures and methods of testing embedded cores. They are also discussing a method for describing core test methods.

Other test standards

Another group of standards related to test technology is under the purview of SCC20 committee. They include:

- IEEE 716 -Std Abbreviated Test Language for All Systems (ATLAS)

- IEEE 993 -Std for Test Equipment Description Language (TEDL)

- IEEE 1226 -A Broad Based Environment for Test -trial use standard (has several parts including S/W interfaces, drivers, test requirements, runtime services)

- IEEE 1232 -Artificial Intelligence exchange and service tie to ATE (AI-ESTATE).

- IEEE 1445 -Standard for Digital Test Interchange Format

- IEEE 1446 -Standard for Ada-based Test Program Development (AdaTPD)

Pat McHugh, TTTC Group Chair, Standards

___________________________________________________________________________________

SCC20 advances broad range of test standards in Anchorage meeting

On May 5-9, 1997 the IEEE Standards Coordinating Committee 20 met in Anchorage, Alaska, for the first of two meetings in 1997. SCC20 gathers semi-annually to work on several standards related to test and maintenance of electronic systems. Best known for maintaining the Abbreviated Test Language for All Systems standard (ATLAS), SCC20 also currently sponsors projects on 20 other standards under the management of six standards-writing subcommittees. The SCC20 standards cover all aspects of board- and system-level test systems.

Throughout the week, the six standards-writing subcommittees and several administrative subcommittees met daily. The following significant events transpired during the meeting.

IEEE 716 Abbreviated Test Language for All Systems (ATLAS). The ATLAS committee worked on two basic areas for future releases of the standard, including a supplement for the 1995 version of ATLAS, covering technical areas omitted from the 1995 ballot, and a revised requirements document for the ATLAS 2000 project. Key elements of ATLAS 2000 include: a hierarchical breakdown of language syntax; closer alignment with other SCC20 standards; and the facilitation of convergence between 716 ATLAS and the airlines' ATLAS (ARINC 626). The subcommittee also worked on comments provided by the International Electrotechnical Commission on the international version of ATLAS (IEC 1926).

IEEE 771 ATLAS User's Guide. The guide, which covers both 716 and 626 ATLAS, is in the negative ballot review phase of the ballot process.

IEEE 993 Test Equipment Description Language (TEDL). The TEDL standard was approved by the IEEE Standards Board in March and the TEDL subcommittee has completed its editorial revisions. The committee is now compiling items for a user's guide.

IEEE 1226 A Broad Based Environment for Test (ABBET). The Overview and Architecture Standard was circulated for ballot as a full-status standard. Based on a change in the approach from initial publication, the number of comments received, and changes required in the draft, the standard is being changed from full status to trial use The Software Interface for Resource Management (1226.3) had been recirculated to ABBET members for comment. The draft has been finalized and has been submitted to the Standards Board for approval. Four projects were canceled due to lack of resources and copyright issues. These projects are P1226.4 Software Interface for Instrument Drivers, P1226.5 Software Interface for Communication Buses, P1226.7 Product Description Interface, and P1226.8 Test Strategy and Requirements. The draft for P1446, Ada Test Program Development (AdaTPD), is nearing completion in preparation for its ballot distribution in early 1998.

IEEE 1232 Artificial Intelligence Exchange and Service Tie to All Test Environments (AI-ESTATE). The subcommittee reaffirmed IEEE Std 1232-1995 as a full use standard at this meeting. The Data and Knowledge Representation standard (1232.1) was approved by the Standards Board as a trial use standard. The Services standard (1232.2) is scheduled to be balloted during the Fall of 1997. (See article, this page, for more about AI-ESTATE.)

IEEE 1389 Standard for the Management of Test and Maintenance Information (TMIMS). This group completed a new requirements document and met during the week for an outline of the draft standard. The group has reorganized its standard by separating services and data representation. An overview and architecture document will be available soon and the data and knowledge representation is in draft form. The subcommittee is actively seeking volunteers with maintenance data collection experience.

IEEE 1445 Digital Test Information Format. This standard has completed the first phase of its ballot and is in the negative ballot review process. The document is expected to be ready for recirculation by the November meeting, and publication is anticipated at the end of 1998.

The next meeting of SCC20 will be at Le Meridien Hotel in New Orleans, LA USA, Nov. 17-21, 1997. For further information, contact William R. SIMPSON, 703-845-6637 (rsimpson@ida.org).

Article submitted by John W. Sheppard, ARINC

___________________________________________________________________________________

AI-ESTATE: Standards for system testability and diagnosis

With the ever-increasing complexity of systems, the need for accurate diagnostic tools is paramount. Unfortunately, the process by which diagnostics and diagnostic tools are currently developed is expensive and error-prone. As a consequence, the AI-ESTATE standards subcommittee has been focusing on developing standards for system diagnosis with the intent of defining a standard mechanism for the exchange of diagnostic information in a wide variety of test contexts. One goal of the standards is to provide a framework within which reliable and accurate diagnostic tools and systems can be built in a cost-effective manner.

Currently the AI-ESTATE team is working on four projects. Project authorization requests (PARs) for the first three have been approved and the fourth is in the investigative stage. P1232 provides the umbrella for all AI-ESTATE work. It corresponds to the definition of an architecture for diagnostic reasoners in test environments. In 1995, the IEEE published the AI-ESTATE overview and architecture standard as IEEE Std 1232-1995 [1]. This standard was published as a trial use standard and was reaffirmed in 1997 as a full-status in standard. P1232.1 defines three information models to be used as the basis of a data exchange format and as formal typing for a set of software services to be provided by a diagnostic reasoner. In 1997, the IEEE Standards Board approved the n AI-ESTATE Data and Knowledge Specification as IEEE Std 1232.1-1997 [2]. This standard is also being published as a trial use standard. P1232.2 defines the software services to be provided by the reasoner. This project depends upon the models of P1232.1 to provide data typing for static (i.e., persistent) data. In addition, P1232.2 includes an information model to address data typing for dynamic data. The current draft of the P1232.2 Service Specification is nearing completion and is expected to be balloted in the Fall of 1997 [3]

AI-ESTATE applications may use any combination of functional elements and interfunction communication. The Service Specification (P1232.2) defines the form and method of communication between components. AI-ESTATE identifies reasoning services provided by a diagnostic reasoner so that transactions between test system components and the reasoner are portable. AI-ESTATE assumes a client-server or cooperative-processing model in defining the diagnostic services.

AI-ESTATE includes two component standards focusing on two distinct aspects of the stated objectives. The first aspect concerns the need to exchange data and knowledge between conformant diagostic systems. By providing a standard representation of test and diagnostic data and knowledge and standard interfaces between reasoners and other elements of a test environment, the costs of test, production, operation, and support will be reduced.

The AI-ESTATE architectural concept provides for the functional elements to communicate with one another via a communications pathway. Essentially, this pathway is an abstraction of the services provided by the functional elements to one another in a client-server architecture.

AI-ESTATE services are provided by reasoners to the other functional elements fitting within the architecture. Reasoners may include diagnostic systems, test sequencers, maintenance data feedback analyzers, intelligent user interfaces, intelligent test programs, etc. The current focus of the standards is on diagnostic reasoners.

Fixing a void in testability metrics

AI-ESTATE has received comments from a wide variety of sources pointing out a void in test standards. Requirements documents and government acquisition documents frequently specify testability requirements for a system, using such language as C. System faults must be capable of being isolated to three or fewer units 98% of the time or the system must exhibit a false alarm rate of no more than 1%. Unfortunately, no standard exists to define the basis for calculating such metrics or for determining that the requirements are being satisfied.

To address this void, the AI-ESTATE subcommittee is exploring the feasibility of developing a standard to address definition and calculation of testability and diagnosability metrics.

The AI-ESTATE standard has been under development for six years under the sponsorship of three IEEE societies the Computer Society, the Aerospace Electronic Systems Society, and the Instrumentation and Measurement Society. Current membership on the subcommittee includes representatives from academia, US military, and industry. The subcommittee also has representatives from several other countries. -Recently, the International Electrotechnical Commission's Technical Committee 93, which focuses on standards for design automation, accepted a proposal to advance the AI-ESTATE standard for fast track standardization at the IEC level.

A number of tool vendors are committed to enhancing or providing tools that conform to the AI-ESTATE standard. Several vendors, including ARINC, Detex, IET, Giordano Associates, Qualitech, and the U.S. Navy, have implemented pre-standard versions of the AI-ESTATE models.

Standardization succeeds only when industry recognizes its need and value. Even with the broad support received so far, help is needed to ensure the standards meet the needs of industry. The AI-ESTATE subcommittee welcomes anyone interested in participating to join and work on the standards. Further information can be obtained from the AI-ESTATE web page at:

http://www.cs.jhu.edu/~sheppard/P1232

or from AI-ESTATE secretary, Greg BOWMAN,

gregory.p.bowman@boeing.com

References

[1] IEEE Std 1232-1995. Trial Use Standard for Artificial Intelligence and Expert System Tie to Automatic Test Equipment (AI-ESTATE): 0 Overview and Architecture.

[2] IEEE Std 1232.1-1997. Trial Use Standard for Artificial Intelligence Exchange and Service Tie to All Test Environments (AI-ESTATE): Data and Knowledge Specification.

[3] IEEE P1232.2. Trial Use Standard for Artificial Intelligence Exchange and Service Tie to All Test Environments (AI-ESTATE): Service Specification, Draft 3.1.

Article by John W. Sheppard, ARINC, jsheppar@arinc.com.

___________________________________________________________________________________

EDITORIAL POLICY

This newsletter is the informal publication of the IEEE Computer Society Test Technology Technical Committee. We will publish all appropriate material although editing may be necessary to meet space or typographical constraints. Articles are not refereed unless so noted. Opinions are those of the contributors and are not necessarily the opinions or positions of TTTC, the IEEE, or the IEEE Computer Society.

Contributors who wish to have their employers name included with their byline must specifically request it with their contribution. Contributors bear responsibility for any issues that may arise with their employer as a result of their contribution.

Editor and Publisher: Ed Thomas

Associate Editor - Mike Keller

Associate Editor, D&T magazine - Don Lenhert

Associate Editor - Europe: Ian Dear

Associate Editor - Asia: Teruhiko Yamada

SEND CONTRIBUTIONS TO:

Ed Thomas, Editor, TTTC Office, PO Box 629, Hollidaysburg, PA 16648 USA. Tel: (814) 941-4669, Fax: (814) 941-4668.

E-mail: eddor@aol.com or tttcnews@aol.com

PREFERRED SUBMISSION FORMAT:

electronic mail in ASCII text format