IEEE Computer Society

Test Technology Technical Committee

Newsletter - November - December 1996

The Newsletter of the Test Technology Technical Committee of the IEEE Computer Society

ZORIAN ELECTED TTTC '97 HEAD

Roy, Nicolaidis win VP spots
New officers will assume posts in January

TTTC announced the results of the recent TTTC 1997 officers elections at the OpCom meeting on October 22 during ITC '96. Yervant Zorian, 1996 Vice Chair, was elected as 1997 Chair. Rabindra Roy was elected 1997 First Vice Chair, and Michael Nicolaidis was elected Second Vice Chair.

As TTTC Chair, Zorian plans to serve the test community by expanding the scope of TTTC to cover the challenging fields of tomorrow's technology, and by strengthening the role of TTTC as a knowledge base and key communication link in the daily life of test professionals. To accomplish this goal, he will initiate programs to: 1. encourage TTTC members from both academia and industry to be involved in initiating and developing technical efforts in the fields of emerging technologies, 2. expand the membership base to include new experts, more students, and wider geographical representation, and 3. strengthen current TTTC conferences, workshops and tutorials to cover a larger base of technical fields and reach more participants.

Zorian, who is well-known to active TTTC volunteers as a seemingly tireless leader and worker involved in many aspects of running TTTC, its activity committees and several sponsored meetings, may not be familiar to the membership at large. In recent years, Yervant has been one of the driving forces behind VLSI Test Symposium where he served as Program Chair (1994 and 1995) and General Chair (1996 and 1997). Another of his interests is D&T magazine where he was Associate Editor-in-Chief from 1994 to 1997, after a stint as BIST Editor. In 1994, Yervant became TTTC Group Chair, Technical Activities. Under his leadership, Group activities and the number of TACs increased dramatically from 5 to 16. Yervant is also active in many other volunteer professional activities within TTTC as well as in other IEEE venues.

On November 8, Zorian joined LogicVision, Inc. where he accepted the position of Chief Technology Advisor. He will be responsible for algorithm research and development for LogicVision's BIST strategy. Before joining LogicVision, Yervant was a Distinguished Member of Technical Staff at Lucent Technologies Bell Laboratories in the Test and Reliability Center at Princeton, New Jersey. Zorian, a recognized authority and leader in BIST, holds a number of US patents in the field. A Senior Member of IEEE, Zorian holds a Ph.D. in Electrical Engineering from McGill University, Canada, as well as an M.Sc. from USC, and an MBA from Wharton. He has published extensively, has received a number of Best Paper awards and holds the AT&T Bell Laboratories Research & Development Award.

Two Vice Chairs elected

1997 will be the first year for TTTC to have two Vice Chairs. This change comes about due to an amendment of the bylaws earlier this year. The amendment added the second vice-chair position because TTTC needs more elected officers to ensure continuity and backup, to manage the elements of a growing TTTC and to attract quality volunteers to a more active role.

First Vice Chair Rabindra (Rob) Roy has a long record of volunteer professional work. In TTTC that record includes leadership positions on the VLSI Test Symposium committees (1993 to 1997) and International Test Synthesis Workshop (1994, 1995). He is a member of the Program Committees of several international conferences and workshops and has been a Program Chair of IEEE VLSI Test Symposium.

Rob is a Research Staff Member at NEC USA in Princeton, New Jersey, where he is pursuing research in various aspects of VLSI, including testing, synthesis for testability, and low-power design. Roy has also worked at AT&T Bell Labs and General Electric Research & Development Center. Rob earned the M.S. and Ph.D. in Electrical & Computer Engineering from University of Illinois. He has received several Best Paper Awards for his work on low power design of DSP circuits and testability of asynchronous circuits. He has over forty publications and five U.S. patents.

The election of Second Vice Chair Michael Nicolaidis adds yet another distinguished person in the international test community to the 1997 TTTC leadership. Michael's TTTC volunteer work includes Vice Chair of Technical Activities (1996) and Chair of the On-Line Testing TAC (1995, 1996). His resume includes service as Program Vice Chair and Program Chair of IEEE VLSI Test Symposium as well as a long list of service to the test profession on many technical program committees. Michael is the founder of the IEEE International On-Line Testing Workshop and served as General Chair of that meeting in 1995 and 1996.

Michael Nicolaidis is a Directeur de Recherche in the French National Research Center (CNRS) and leader of the Reliable Integrated Systems group in the TIMA Laboratory, Grenoble. He holds the EE degree from the University of Thessaloniki (Greece) and the Engineer Doctorate Thesis from the National Polytechnic Institute of Grenoble (France). His research interests include testing of VLSI systems, on-line testing, self-checking and fail-safe systems, DFT, BIST, IDDQ testing, radiation hardened/tolerant systems. Nicolaidis has published more than 90 technical papers in these domains and holds several patents.

The newly elected team will take the reins of TTTC on January 1, 1997. TTTC Newsletter will publish a complete list of volunteer appointments to the 1997 Operations Committee in the January - February, 1997 issue.

FAREWELL FROM THE 1996 CHAIR

Since this is the last issue of our Newsletter for 1996 and the final during my tenure as your Test Technology Technical Committee Chair, I want to take this opportunity to thank you for your valuable support of our activities during 1996.

As chair of your committee for the past two years I have enjoyed working with you. Thanks to your efforts, our membership has grown 25%, and our technical programs have broken all previous records. This year has been very busy and particularly fruitful. Among our many world-wide activities we sponsored or co-sponsored two conferences, two symposia, seventeen workshops and two tutorial programs. Final reports are still being received at this time, but every indication is that all of our activities were not only technically excellent but financially rewarding. Based on current plans, 1997 promises to be another very busy year.

At the end of this year, I shall pass on the responsibilities of Chair to Yervant ZORIAN whom you elected for 1997. I know of no more capable and dedicated person to serve you. But he cannot succeed without the help of many volunteers. He needs and deserves your participation. Activities increase each year but unfortunately volunteerism is waning. We need new people to get involved and become tomorrow's leaders. I encourage each of you to get in touch with Yervant or his committee members to find out how you can become involved. You will find the experience of participation very rewarding, both professionally and socially.

Fred Liguori, TTTC Chair, ffliguori@aol.com

** ISSUES IN TEST **

Asynchronous circuits:
Cool, fast and testable

By Eric Bruls, brulse@natlab.research.philips.com, and Marly Roncken, Philips Research Labs

For as long as VLSI digital circuits have existed, good design has meant synchronous design, where a global clock signal determines the pace of logical switching activity and takes care of overall synchronization. This rigid design style has facilitated the development of efficient design synthesis methods and tools and structured test techniques. As such, synchronous VLSI design is supported by mature CAD and CAT, enabling the level of integration we see today.

Synchronous circuits have their problems, however. The periodic clock causes periodic bursts of power consumption, generating electromagnetic radiation at harmonics of the clock frequency. And global clocking causes power consumption even in those parts of the circuit that are not in use at any particular time. Anyone can observe these issues in the every-day usage of electronic equipment. Problems with electromagnetic compatibility (EMC), for example, make it necessary to refrain from the usage of electronic equipment, such as lap-tops, during take-off and landing of an airplane. Another well-known problem is the power consumption in wireless phone communication, which results in relatively short stand-by times for this equipment.

Asynchronous design has long been foreseen as the white knight that will rescue products that require high speed, EMC and low-power consumption. But, until recently, asynchronous design lacked effective methods and tools, making it virtually impossible to use the technique at large scale. Asynchronous circuits have also been notoriously difficult to test. These and other difficulties have limited asynchronous designs to niche applications in the past.

The situation is changing, however, as more and more companies realize that asynchronous circuits can solve speed, power and EMC problems and the barriers to their use can be overcome. As a result, companies like Intel, Sun, and Philips are increasing their efforts in asynchronous design. This trend was reflected in ITC '96, which presented a technical paper session and an animated panel session on asynchronous design and test issues.

A local clocking or synchronization strategy instead of a global one provides potential performance advantages in operating speed, power consumption, and EMC. Operating speed is limited with a global clocking strategy because clock speed can be no faster than the overall worst-case situation requires, but an asynchronous approach allows for local evaluation and optimization.

With respect to power consumption, especially important for portable applications, a global clock signal induces global activity and global power dissipation, even if only part of the IC is actually functioning at that moment in time. A local clocking strategy is preferable for these applications. Though clock-gating would partially address this issue for synchronous circuits, it does not provide the fine-grained modularity offered by asynchronous solutions. A similar observation can be made for Multi-Media applications, which typically combine multiple data and clock rates, and hence locally different operating speeds.

For EM radiation, a global clock implies that all activity in the IC is synchronized, which means that all radiation is concentrated in time and frequency, resulting in a worst-case scenario. An asynchronous design style inherently causes the radiation energy to be distributed more evenly.

There are two main styles of asynchronous design. The first style, used by Philips and Manchester University for example, primarily focuses on low power and good EMC performance. For such applications, a design style based on handshake signaling has been developed. It is supported by dedicated and proprietary design synthesis tools and allows for fast design of complex VLSI circuits. In addition, the testability of such circuits has been investigated in depth, resulting in a DFT approach which can be automated and which enables simple Automatic Test Pattern Generation (See ITC '96 Proceedings, papers 8.1 and 8.2).

The second design style, pursued by Intel and Sun, aims primarily at improved speed performance. For example, Intel's asynchronous version of their x86 microcontroller shows a speed increase by a factor of three. Design synthesis and test strategies for such applications are still under development. It should be noted that design and test synthesis is also notoriously difficult for high-performance synchronous ICs and requires dedicated solutions.

Concluding, we note that asynchronous circuits provide some interesting advantages over synchronous ones. On the other hand, asynchronous design is not yet fully mature and still lacks support by commercial CAD and CAT vendors. Recent developments, however, prove the feasibility and it seems just a matter of time for asynchronous to enter the commercial arena, this time to stay.

** Issues in Test **
MOS SCALING AND IDDQ

Manoj Sachdev,
sachdev@natlab.research.philips.com

Editor's Note: In the last issue, we featured an article questioning the future of IDDQ testing. Here's another view.

Semiconductor technology is advancing at a breath-necking pace and there seems to be no fundamental reason to arrest its pace in near future. The technology's growth is largely fuelled by the ability of the MOS transistor to scale. Scaling offers many technical as well as commercial advantages. These advantages include higher level of integration, higher operational frequency, reduced power consumption, cheaper manufacturing, etc.

If one studies the evolution of MOS technology, low power consumption, active as well as static, has been the crucial and often the overriding parameter. In late 70s and early 80s, despite its lower packing density, slower operational frequency, CMOS displaced NMOS as the prime technology owing to its lower power consumption. Ever since then, researchers have managed to reduce power consumption with each successive scaled generation. Even today, low power design/technology issues are receiving unprecedented attention.

MOS Scaling and IDDQ

As the scaled devices approach deep sub-micron region, device reliability and low power constraints enforce a reduction in power supply voltage which in turn necessitates lower transistor threshold voltage. Reduction in threshold voltage, VT, results in increased off current. For example, if the VT of n-channel transistor is moved from 0.6V to 0.3V, its off current is increased by a factor 103 or 104 . Such an increase with an ever increasing number of transistors has serious consequences for low power applications as well as IDDQ testing.

It is fair to say that, for state of the art VLSIs today, static power consumption, and hence quiescent current, is still a small fraction of total power consumption. In spite of this, many technological, circuit level, test level solutions have been proposed to reduce static power consumption with the objectives: I. to reduce power consumption, and II. to sustain and enhance the effectiveness of IDDQ testing in deep sub-micron. The effectiveness of these solutions have been amply demonstrated with 104 times or more reduction in quiescent current on real-life circuits. Owing to the brevity of space, it is not possible to name all of them: an interested reader may look into the proceedings of various design, process, and test conferences.

Testing in Deep Sub-micron

Finally, we should address some general issues of testing deep sub-micron devices. No matter which test methodology - IDDQ, Boolean, etc. - is used, these devices will be much more difficult to test. Unfortunately, a lower VT also means a drastic reduction in logic noise margins. Lower logic noise margins together with high frequency of operation and longer interconnects will further reduce the effectiveness of already beleaguered SA fault model.

The deep sub-micron IDDQ will always be there, however with a difference. In the future, one has to invest in DFT to extract full IDDQ benefits. DFT is an accepted overhead in Boolean testing: why should it not be in IDDQ testing? Finally, it is needless to say that both test methods will be needed to achieve quality/economics objectives.

ITC 1996: the view from the Program Chair

The technical program of International Test Conference 1996 focused particularly on the test challenges presented by the incredible complexity of the devices we see on the horizon. From the opening salvos in the Plenary to the closing panel discussions, visions of ten million gates and the four kilometers of wiring needed to connect deep submicron devices dominated discussions.

There were several significant undercurrents at ITC '96:

First, design complexity has outstripped available tools, particularly in the area of interconnect parasitics. Parasitic coupling to the substrate has been acceptably modeled, but line-to-line coupling, interconnect resistance, and interconnect inductance are not handled by today's tools. Papers presented in ITC's Design Validation Seminar highlighted these and other difficulties, and pointed out that, from the interconnect standpoint, the standard definition of min-max corners is probably inadequate.

Second, current resolution in IDDQ measurements is under sharp stress as we go into deep submicron designs. This may impact design rules in a strong way. It may be necessary to design devices with separable power structures in order to make valid IDDQ tests at all.

Third, more significant results are coming from the BIST area. While it is a bit early to say that BIST is becoming routine, embedded test structures for a variety of embedded cores are available and well known to designers. Implementing ULSI devices using core designs from a variety of sources will depend on verifiable, testable cores.

ITC '96 also expanded its practical application offerings. 1995's highly successful Lecture Series on PCB unpowered opens testing was expanded to include newer techniques. In addition, fault isolation and diagnosis played to a standing-room-only crowd in a 2nd Lecture Series.

A collage of well-attended panels closed the conference. Ranging from the ever present IDDQ to the perennial question "Why does ATE Hardware Cost So Much?", these panels kept audience interest at a peak.

Burnell West, ITC '96 Program Chair, west@san-jose.ate.slb.com

ITC Test Week(tm) event:
IDDQ TEST WORKSHOP PLAYS TO CAPACITY CROWD

The Second IEEE International Workshop on IDDQ Testing (IDDQ'96), sponsored by the IEEE Computer Society and the Test Technology Technical Committee, was held in Washington DC in conjunction with the International Test Conference and the Test Week. The workshop was attended by a capacity crowd of 160 participants, representing both industry and academia.

The workshop started on the evening of October 24 with a Keynote address by Bob Grabble, Test and Development Manager for ASIC Engineering Services at Texas Instruments. Bob traced the history of IDDQ testing at TI and shared his insight on IDDQ testing. Bob's address set the stage for the first technical session on the effectiveness of IDDQ testing, which was followed by an open-mike session. The evening was completed with a social reception held jointly with the Test Economics Workshop.

On October 25, the workshop offered four technical sessions on Testing and Testability, Limit Setting, Current Sensors and Test Generation. The workshop concluded with a panel session. One of the noteworthy features of the workshop was the wide audience participation in discussions after each presentation.

A survey completed by attendees at the end of the workshop indicated that an overwhelming majority (84%) would like the next workshop to be held in conjunction with the International Test Conference in 1997. 54% of the participants indicated that they like the present duration of the workshop (1 1/2 days) while 38% wanted a one day workshop. In terms of theoretical/practical balance, 9% felt that more coverage on theory/research is needed, while 46% would prefer a higher coverage on practice, with the rest agreeing with the present balance. 70% of the participants indicated that they like the current mix of discussions and presentations.

A. Jayasumana, G. Chair, jayasuma@lance.colostate.edu

ITC 1996: IN TEST, 'ONE-SIZE-FITS-ALL' DOESN'T FIT

ITC plenary session addresses the implications of SIA Roadmap

"There is no one-size-fits-all test solution" according to ITC Keynoter Wally RHINES, President and CEO of Mentor Graphics Corporation. Dr. Rhines introduced his plenary session address by re-stating the key points of the SIA Technology Roadmap, emphasizing its implications on both the design and test communities. The driver of the electronics industry will be yet more re-use to increase design productivity - "10X improvement in gates designed/person-month between 1994 and 1999".

He also showed the inexorable rise of software as part of system design and claimed that, in any system company, including those in the ATE industry, more than 50% of the R&D people are software designers. His conclusions: at this point, more emphasis on systems design, as opposed to hardware design and software design, is needed. In addition, test problems become acute as the word "system" becomes more and more ambiguous: are systems chips, boards, or collections of boards? The solution: continue the development of integrated system development environments, including the verification of design and manufacturing of combined hardware/software products.

Rhines then turned his attention to the requirements of the future. He predicted increased use of re-usable Intellectual Property coming from multiple sources, focusing on a pro-active design-for-test methodology as the only viable test solution -- re-iterating that "no one size fits all". DFT will come in many flavors, tailored to address specific design functionality including: embedded memory arrays, control logic, arithmetic functions, datapath, micro-processors, DSPs, and even analog and mixed-signal. Indeed, he claimed that analog and mixed-signal DFT will be the hardest of all to realize with "no top notch commercial solution within the next 5 years. The first problem to solve is devising a suitable metric in order to judge the efficacy of an analog test."

In conclusion, Dr. Rhines said that there will be no shortage of test challenges in the future. Solutions will be many and varied and they all will have to play in an integrated hardware/software design environment.

WILL TEST BLOCK THE ROAD?

Wojciech Maly's invited plenary address, "New and not-so-new test challenges of the next decade," focused on the impact of the SIA Technology Roadmap on test and design-for-test practice in the semiconductor industry. The Roadmap is predicting devices containing hundreds of millions of transistors and operating at GHz clock speeds by the year 2010. Dr. Maly, professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University, posed the question, " How will we contain and manage the test problems associated with such devices?"

Maly's thesis: test problems can only be contained by massive application of both old and yet-to-be-invented design-for-test techniques. External ATE will not be able to keep up with the need to test devices "at speed" in order to catch deep sub-micron speed-related defects. New forms of BIST, capable of testing tomorrow's technology at tomorrow's speeds, must be developed. Even more fundamental, there will be a new set of manufacturing defects. Understanding the nature of these defects will underpin new approaches to future test measurement techniques and DFT styles.

Moreover, time-to-market pressure increases remorselessly placing even greater pressure on those concerned with design validation, prototype debug, and effective monitoring of the manufacturing processes.

Maly's conclusion: if the DFT and test communities do not start re-thinking the fundamentals of test, we could get the blame as the major reason why the aspirations of the SIA could not be achieved.

B. Bennetts, ITC Program Vice Chair, benb@lvision.com

At ITC Test Week (tm):
ITC CROWDS VIEW NEW 1149.4 CHIP

In-Circuit, Mixed-Signal Test without a Bed-of-Nails

At ITC '96, teams from Hewlett-Packard and Matsushita Electric Industries demonstrated, for the first time ever, working silicon containing P1149.4 structures in a test IC and showed how the new devices could be used to test wire interconnects and external discrete analog devices on boards.

The MEI team, Katsuhiro Hirayama, Kozo Nuriya, and Akira Matsuzawa, created the P1149.4 Test IC in record time, starting layout in May of 1996 and delivering working, tested silicon to HP in early September.

The HP team, John McDermid, Rod Browen, and Ken Parker, built a test fixture incorporating the new IC and interfaced it to an existing board test ATE system (an HP-3070). New software was written to implement P1149.4 analog metrology and 1149.1 interconnect tests on the ATE system. All of this was completed "just in time" for a demonstration proving the P1149.4 concepts at ITC in October.

The HP and MEI teams had been informing the P1149.4 Working Group of their progress since late September, so the WG agreed to a meeting and demonstration at ITC. MEI hand-carried a number of their ICs, mounted on small boards, to ITC to give to the WG members. The ICs included complete documentation, which was not completed until 2:00 am on the day of their flight. The HP team packaged their demo fixture at 4:00 pm the day before their flight.

Both the IC structures and the test methodologies were taken from the 1993 ITC Best Paper, "Structure and Metrology for an Analog Testability Bus." The Analog Boundary Module (ABM) was virtually identical to that described in the paper, and is quite close to the current concept of the P1149.4 Working Group. The MEI team also added unique testability structures to the 2-wire analog test port (AT1, AT2) that allow the 1149.1 interconnect software to test this port for shorts/opens along with all other mission digital/analog pins. This makes it possible to test the analog testability infrastructure at the board level at digital speeds.

At the WG meeting, held on Sunday, October 20, MEI gave a presentation on their new IC and then passed out boards to interested WG members. About 20 were distributed at the meeting. The HP team then announced their working demonstration (viewable in the HP booth on the exhibit floor) of every 1149.4 feature described in the 1993 ITC paper. With just this announcement in the meeting, followed by word-of-mouth spreading through the conference, the P1149.4 demo was literally mobbed. John McDermid gave non-stop demonstrations for virtually the entire conference, with people lined up three deep around the testhead. Another eight boards were given to researchers during the demonstrations.

The HP team demonstrated the ability to detect, with unmodified 1149.1 interconnect test software, wiring shorts/opens among analog pins, digital pins and the analog testabilty port. Then, they demonstrated tests of discrete components, including resistors, capacitors and inductors. Analog measurements of better than 1% accuracy were demonstrated on silicon switches with impedances in the 1.6 Kohm range.

Both teams, along with other 1149.4 WG members, will proceed with further studies. Matsushita asked for no compensation for the thirty 1149.4 IC boards that they generously distributed except that the recipients report their research to the P1149.4 Working Group.

The demonstration at the HP booth attracted an unprecedented amount of attention. "In my 21 years in this business, I've never seen so much interest in a demo," Parker reported. "This may indicate that mixed signal test problems are looming large for more than just the P1149.4 Working Group."

K. Parker, parker@lvld.hp.com

At ITC Test Week(tm):

ITC PROGRAM COMMITTEE MEETS WITH EUROPEAN AND ASIAN ATTENDEES IN PROGRAM IMPROVEMENT EFFORT

The ITC Program Committee hosted two meetings during ITC '96 aimed at gaining a better understanding of ITC attendees from Europe and Asia and what ITC could do to enhance the ITC experience for these attendees. Separate meetings addressed European and Asian attendees. The stated objective of both meetings was to give ITC attendees from Europe or Asia an opportunity to interact with the ITC Program Committee and Steering Committee and to voice their opinions and suggestions about how ITC is organized and managed. Both forums were held on the evening of October 23.

The Asian Forum was chaired by Masaaki YOSHIDA and moderated by Burnie WEST. Mr. Yoshida is Asian Chair of the ITC Program Committee, while Burnie is the Program Committee Chair. Thirty-three people, mostly test professionals from Asia attended the forum. Japan, Korea and China were represented in the attendance.

The European Forum was chaired by Christian LANDRAULT and moderated by Ben BENNETTS. Christian is the European Vice Chair and Ben is Vice Chair of the ITC Program Committee. Both are well-known in the European test community. Twenty-three people participated in the forum.

Many suggestions made: travel cost an issue for overseas attendees

Active discussion was the order of the day in both meetings. Following are points raised in the meetings:

The challenges of higher integration, a hot topic that threaded through ITC '96, also was a mainline topic in the Asian Forum. Other topical issues:

Courtois, Rencz propose Thermal Testing TAC

At the recent TTTC meetings during ITC '96, Bernard COURTOIS and Maria RENCZ proposed a Technical Activity Committee on thermal issues. Here is their proposal.

Decreasing dimensions of ICs and increasing density of packages make thermal issues more and more important. The scope of the proposed TAC is to enable the exploration of thermal tools, mechanisms, sensors in view to implement Design for Thermal Testability.

MOTIVATION

With silicon microtechnology, designers intend to realize electrical networks: these are the integrated circuits. This goal, however, can never be obtained solely - a thermal network is also necessarily generated. The electrical parts dissipate heat, this is the source of the thermal network. As a result, the temperature of the chip increases, changing the electrical parameters. In some cases, this can even result in burning out the elements. With decreasing chip feature sizes and package dimensions, with the increasing integration density, the heat production per unit volume increases - continuously enlarging the severity of these problems.

This is why during the design of an integrated circuit concentrating only on the electrical operation is no longer sufficient. Today, we also have to manage the thermal network; overheating and electrical-thermal cross couplings have to be impeded. We need methods to calculate and measure the temperature distribution on the chip.

According to recent statistics, the largest part of field detected failures are originated from overheating, due to inappropriate thermal design. Thermally originated malfunctions can be prevented by on-line thermal monitoring. This can be accomplished by thermal sensors integrated in the chip, connected to an evaluator and actuator circuitry.

The above-mentioned important subjects are not appropriately represented in today's conferences, workshops, or technical journals today. The only existing forum to discuss these subjects is the THERMINIC Workshop, created by the proposers two years ago.

ACTIVITIES

The proposers are already involved in a number of activities including the organization of two THERMINIC Workshops. THERMINIC Workshops are events to discuss the essential thermal questions of microelectronics and microstructures.

The first THERMINIC Workshop was held in Grenoble in 1995. It brought together about 90 attendees from Europe, the USA and Japan. Two Special Issues of Journals resulted from the 1995 workshop, one in the Microelectronics Journal and the other in the Journal of Sensors and Actuators.

The second THERMINIC Workshop was held in Budapest in September 1996. The workshop received over 60 submissions, much more than in 1995. 34 technical papers and 15 posters were accepted. Again the workshop will spawn special Issues of two journals: the Microelectronics Journal and IEEE Transactions on VLSI. The 1996 Workshop is co-sponsored (50%) by TTTC, in cooperation with ETTTC.

We also expect to submit a panel proposal to VLSI Test Symposium 1997.

By Bernard Courtois, bernard.courtois@imag.fr and Maria Rencz

TTTC MEETING AT VLSI TEST SYMPOSIUM

All TTTC members are welcome to attend TTTC's Operations Committee meetings. The next meeting will be held at VLSI Test Symposium, Hyatt Regency Monterey Hotel in Monterey, California USA, April 27-30, 1997. All TTTC meeting and TAC chairs should prepare written reports for the meeting. Watch for a meeting schedule and agenda.

NEW COORDINATES

Changing Positions/Addresses

Yervant Zorian, has accepted the position of Chief Technology Advisor at LogicVision, Inc. His new coordinates are : Yervant Zorian, Ph.D., LogicVision, Inc., 31B Chicopee Drive, Princeton, NJ 08540 USA. Tel: (609) 497-1744, Fax: (609) 497-1754, E-mail: zorian@lvision.com

Doris and Ed Thomas, are retiring from running the ITC Office, but will continue to operate the TTTC Office. The coordinates of both offices will change. The ITC Office will be managed by Pamela Wagner, of Courtesy Associates. The new office coordinates are listed below. They will be effective January 1, 1997.

TTTC Office: Test Technology Committee, P.O. Box 629, Hollidaysburg, PA 16648 USA. Tel: (814) 941-4669, Fax: (814) 941-4668. E-mail: EdDor@aol.com

ITC Office: International Test Conference, 655 15th St. NW, Suite 300, Washington, DC 20005. Tel: +1-202-639-4164, Fax: +1-202-347-6109

Keep in touch! If you are changing your position or address, please let us know. We plan to make this a regular feature of TTTC Newsletter.

EDITORIAL POLICY

This newsletter is the informal publication of the IEEE Computer Society Test Technology Technical Committee. The newsletter will publish all appropriate material although editing may be necessary to meet space or typographical constraints. Items are not refereed unless so noted. Opinions are not necessarily the opinions or positions of TTTC.

Editor and Publisher: Ed Thomas
Associate Editor - Europe: Ian Dear
Associate Editor - Asia: Teruhiko Yamada

SEND CONTRIBUTIONS TO:

Ed Thomas, Editor, TTTC Office, P.O. Box 629, Hollidaysburg, PA 16648
Tel: (814) 941-4669, Fax: (814) 941-4668.
E-mail: tttcnews@aol.com

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