Awards

THE TTTC JAMES BEAUSANG STUDENT AWARD FOR DFT

To encourage student participation and recognize excellence in the field of design for testability, the IEEE Computer Society Test Technology Technical Council (TTTC) established the TTTC James Beausang Student Award for DFT.

This Award honors the memory of Dr. James Beausang, a well-known researcher and practitioner in Design for Testability and Test Synthesis. The Award endowment came from private, corporate and IEEE funding.

The TTTC Beausang Award was granted exclusively to undergraduate or graduate student(s) listed as primary authors of a qualifying paper. Only papers accepted at the VLSI Test Symposium or the International Test Conference qualify. The paper content may be derived from university or industrial research and development. Eligible subject areas include test architectures, synthesis and analysis research applied to Scan, Design for Testability, Test Synthesis, BIST, Boundary Scan and Embedded Core Test. The Award was granted four times: VTS 1999, ITC 1999, VTS 2000, and ITC 2000.

Winners of the Award were:

• VTS-1999: Hyungwon Kim, University of Michigan - Lead author of the paper H. Kim and J. P. Hayes, "Delay Fault Testing of Designs with Embedded IP Cores"



• ITC-1999: Jayabrata Ghosh-Dastidar, University of Texas at Austin , Lead author of the paper J. Ghosh-Dastidar, D. Das and N. Touba, "Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information"



• VTS-2000: Anshuman Chandra, Duke University, USA : "Test Data Compression for System-On-A-Chip using Gulomb Codes"



• ITC-2000: Nicola Nicolici, University of Southampton, England, Lead author of the paper N. Nicolici and B. M. Al-Hashimi "Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths"

The Award benefits to the author(s) are:

For further information, please contact: Dr. Ken Wagner