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Test Technology Technical Council Home Page Directory
Test Technology Technical Council Home Page Directory
| Test Technology Technical Committee Member | General Areas of Technical Interest | |
| Miron Abramovici, CTO - DAFCA, Inc. | digital system testing and testable design, reconfigurable computing | |
| John M. Acken , Intel | encryption, digital watermarking, convergence of computing and communication, digital security, data integrity, electronic identification, web based everything, IC Testing, IDDQ testing, Fault Modeling, CMOS design, Logic Synthesis, Verification, DFT, fault tolerant security issues, and Whirled Peas | |
| Rob Aitken , Hewlett-Packard Co. | DFT, IDDQ testing, fault diagnosis, synthesis for testability, fault modeling and test effectiveness | |
| Hussain Al-Asaad , Assistant Professor, Department of Electrical and Computer Engineering, University of California, Davis | Design verification, testing, fault-tolerant computing | |
| Kurt J. Antreich , Professor and Head, Institute of Electronic Design Automation, Technical University of Munich | logic and architecture synthesis, analysis and optimization of analog components, layout synthesis, simulation and verification, test pattern generation | |
| Prof. Dr. Erich Barke , University of Hanover, Hanover, Germany | EDA, Verification, Test, Fault Emulation | |
| Bernd Becker , Institute of Computer Science, University Freiburg | test (ATPG, DFT), synthesis, verification of VLSI circuits | |
| Dr R G "Ben" Bennetts , Bennetts Associates | DFT, Boundary Scan, BIST, Scan | |
| Melvin A. Breuer , Charles Lee Powell Professor of Computer Engineering, University of Southern California | Built-in self-test, design-for-test, ATPG, crosstalk "faults", intelligible testing, application oriented testing, effective yield | |
| Kenneth M. Butler , Texas Instruments | ATPG, design for test, fault and defect modeling, automated diagnosis, test quality, test economics | |
| Krishnendu Chakrabarty , Assistant Professor of Electrical and Computer Engineering, Duke University | SoC Test, BIST, distributed sensor networks, embedded RTOS, architectural optimization of microelectrofluidic systems | |
| Shih-Chieh Chang , National Chung-Cheng University, Taiwan, R.O.C. | Design for Test, ATPG, BIST | |
| Professor Kwang-Ting (Tim) Cheng , University of California, Santa Barbara | VLSI Testing, Verification and Synthesis | |
| Bruce F. Cockburn, Ph.D. , University of Alberta, Edmonton, Canada | memory test, BIST, design for testability, multilevel DRAM | |
| Fulvio Corno , Politecnico di Torino, Torino, Italy | ATPG, BIST, Testable Synthesis, Formal Verification | |
| Bernard Courtois , TIMA/CMP | Testing circuits and systems, analog and mixed-signal testing, thermal testing, MEMS testing | |
| Peter Dahlgren , Associate Professor, Chalmers University, Sweden | Fault simulation, ATPG, Transistor-level fault modeling, Logic simulation/validation, Error-detection | |
| Joe Damore , Senior Technical Staff Member, IBM, DATC Newsletter Editor and Secretary | Computer oriented techniques in all aspects of the design process of computers and electronic systems, with particular emphasis on design languages, logic synthesis, verification techniques, manufacturing interface data, graphics and database management; Design Automation Technical Committee | |
| Sujit Dey , Dept. of Electrical and Computer Engineering, University of California, San Diego | Design, Validation and Test for Hardware-Software Embedded Systems, Design and Test for Ultra Deep Sub Micron, VLSI CAD | |
| Martin H. Eastburn , Mitsubishi Electronics America, Inc. | Memory devices, DIMMs, DRAMS, IC and Module designs. | |
| Khaled Elleithy , Associate Professor, King Fahd University, Dhahran, Saudi Arabia | CAD, Formal Verification, High Level Synthesis | |
| Michele Favalli , DI - University of Ferrara | IC's design, simulation and testing, Self-checking and fault tolerant circuits | |
| F. Joel Ferguson , Associate Professor, University of California at Santa Cruz | DFM/DFT of modern IC technologies, Defects in CMOS ICs, Fault models | |
| Paulo Flores , IST/INESC - Technical University of Lisbon, Portugal | ATPG, BIST, Test optimization, Formal Verification, VHDL Synthesis | |
| W. Kent Fuchs , School of Electrical and Computer Engineering, Purdue University | Diagnosis and Failure Analysis -- CAD Tools for Testing and Failure; Analysis in Integrated Circuits; Recovery from Failures -- Mobile Computing, Active Networks, High Performance Computing | |
| Prof. Franco Fummi , Dipartimento di Informatica, Universita` di Verona | automatic test pattern generation, functional testing, BIST | |
| Hideo Fujiwara , Nara Institute of Science and Technology (NAIST), Nara, Japan | Test Generation, Design for Testability, (High Level/Logic) Synthesis for Testability, Built-In Self-Test | |
| Clay Gloster, Jr. , PhD, PE, Professor, North Carolina State University | Reconfigurable/Adaptive Computing, High Performance Digital Signal Processing, Design for Testability, Built-In Self-Test, and Partial Scan | |
| Dr. Robert B. Grafton , Program Director, Design Automation Program in the C-CR Division, National Science Foundation | VLSI Design Automation and Manufacturing test | |
| Arne Halaas , Professor, Dept. of Computer and Information Science, Faculty of Physics, Informatics and Mathematics, Norwegian University of Science and Technology | HW/SW solutions for high-performance search engines | |
| Dong S. Ha , Associate Professor, Virginia Tech | ATPG, Fault Simulation, Test Synthesis | |
| John P. Hayes , University of Michigan |
(1) Digital System Design: testing methods, built-in self-test (BIST), design
verification, logic synthesis, computer-aided design (CAD) techniques.
(2) Computer Architecture: reliable/fault-tolerant systems, parallel processing, embedded architectures. (3) VLSI (Very Large-scale Integrated) Circuits: physical design and layout techniques, systems-on-a-chip. |
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| Sybille Hellebrand , Division of Computer Architecture, University of Stuttgart | BIST, Synthesis for BIST, on-line test | |
| Michael Hsiao , Assistant Professor, Department of Electrical and Computer Engineering, Rutgers University | Computer-aided design and design automation, VLSI Testing, Design Verification, Fault Diagnosis, Design for Testability | |
| Jiun-Lang Huang , Research Assistant, ECE Department, UCSB | VLSI testing, analog/mixed-signal fault simulation, testing, and BIST | |
| Axel Hunger , Prof. Dr.-Ing., University of Duisburg | test, simulation, multimedia, curriculum design | |
| Andre Ivanov , Department of Electrical and Computer Engineering, University of British Columbia | Areas of interest: analog and mixed signal testing, BIST, DFT (analog and digital) | |
| Vikram Iyengar , University of Illinois at Urbana-Champaign | BIST, Embedded-core test, Design Verification of Microprocessors. | |
| Axel Jantsch, , Associate Professor | System level design and validation, HW/SW Codesign | |
| Niraj K Jha, Ph.D. , Princeton University, Princeton, NJ 08544 | Test generation and design for testability at register-transfer, behavior and system-on-a-chip levels. | |
| Neil Kelly , Chief Technologist, LTX Corporation, Westwood MA | Mixed signal test, Windows software | |
| Haluk Konuk , Ph.D., Hewlett-Packard, Palo Alto, CA | Defect modeling, delay testing, DFT, fault(defect) simulation, ATPG | |
| David L. Landis , Ph.D., P.E., The Pennsylvania State University, University Park, PA | Digital System Design and Test, Rapid System Prototyping | |
| Ron Leckie , INFRASTRUCTURE | Test Technology, Test Hardware, Test Software, and Technology Marketing. | |
| Donald H. Lenhert , Professor of Electrical & Computer Engineering, Kansas State University | Testing of digital systems; built-in self-test; IDDQ testing; microprocessor applications | |
| Dr. Karen Panetta Lentz , Dept of Electrical Engineering and Computer Science, Tufts University | Simulation, fault simulation and multimedia | |
| Martin Margala , Ph.D., U. of Alberta, Edmonton, AB, Canada | Low-Power Low-Voltage Mixed-Signal Design and Testing, VLSI | |
| Joao Marques-Silva , Technical University of Lisbon, IST/INESC/CEL | Test Pattern Generation and Optimization, Problems in Testing, Application of Discrete Optimization Models and Algorithms to Design Automation, Boolean Satisfiability and Integer Optimization | |
| Meryem Marzouki , Researcher with the CNRS, LIP6/ASIM Lab., Paris, France | System Test and Diagnosis, Synthesis for Testability, SoC Testing | |
| Dr.-Ing. Wolfgang Mertin , University of Duisburg | Development of contactless test systems for circuit internal tests (EBEAM, E.-O.Sampling, Scanning Force Microscopy, Scanning Nearfield Optical Microscopy) | |
| Assoc. Prof. Liviu Cristian MICLEA, Ph.D. , Tech. Univ. Cluj-Napoca, Romania | DFT, CAE, ATPG | |
| Cecilia Metra , DEIS - University of Bologna | hardware fault-tolerance, on-line testing, self-checking circuit design, FPGA testing, low-power designs | |
| Subhasish Mitra , Center For Reliable Computing, Stanford University | Digital testing and design/synthesis for testability, Logic synthesis, Fault-tolerance and Reconfigurable systems. | |
| Professor Takashi Nanya , University of Tokyo, Tokyo, Japan | Fault-Tolerant Computing, Concurrent Checking, Asynchronous Circuits/Systems Design | |
| Victor P. Nelson , Auburn University | EDA, MCM Test, DFT, Computer Architecture | |
| Phil Nigh , Test Development Engineering, IBM Microelectronics | defect-based testing, test methods, structural/functional testing, BIST, reliability screening, fault diagnosis | |
| Franc Novak , Jozef Stefan Institute, Slovenia | test and diagnosis, DFT, BIST, mixed-signal test | |
| Ondrej Novak , Technical University of Liberec, Czech Republic | BIST, test pattern generation, linear codes | |
| Prof. Zebo Peng , Linkoping University, Sweden | design and test of embedded systems, design for testability, test synthesis, and hardware/software co-design. | |
| Vincenzo PIURI , Department of Electronics and Information Politecnico di Milano | computer architecture, computer arithmetic, parallel and distributed systems, neural network architectures, fault tolerance in arithmetic systems, coding, high-level synthesis, fault tolerant computing, fault tolerant distribute file systems, soft computing, neural networks for signal/image processing, neural networks for identification and control. | |
| Irith Pomeranz , Electrical and Computer Engineering Department, University of Iowa | Test generation, fault diagnosis, design-for-testability, built-in self-test, synthesis and verification of VLSI circuits. | |
| Anand Raghunathan , Research Staff Member, NEC USA C&C Research Labs | ATPG, DFT, System-on-Chip testing, design validation | |
| Professor Robert Redinbo , Department of Electrical and Computer Engineering, University of California | Fault-tolerant computing, testing, protecting high-speed signal processing and application specific integrated circuits, testing and protection of error-correcting and detecting circuits | |
| Gordon Roberts , Department of Electrical & Computer Engineering, McGill University | Mixed-Signal Testing, Mixed-Signal BIST, Analog and Mixed-Signal IC Design | |
| Gordon D Robinson , Sr Member Technical Staff, Credence Systems Corporation | ATE, Software, Design and Test Cooperation | |
| Dan Romanchik , Technical Writer and Editor | ATE, instrumentation, ham radio, bicycling | |
| Elizabeth M. Rudnick , University of Illinois, Urbana, IL | ATPG, design verification, fault diagnosis, DFT, VLSI design automation | |
| Jacob Savir , New Jersey Institute of Technology | Test generation, Fault Simulation, Built-In Self-Test, Design for Testability | |
| Prof. Micaela Serra , Dept. of C SC, Univ. of Victoria, Victoria, B.C., Canada | Testing, Hardware/Software Codesign | |
| Sharad Seth , University of Nebraska-Lincoln | design verification, synthesis for testability, tester data analysis for device quality estimation | |
| Piotr R. Sidorowicz M.A. , University of Waterloo, Waterloo, ON N2L3G1 CANADA | Memory Testing, Asynchronous Circuit Design | |
| Dr. Matteo Sonza Reorda , Politecnico di Torino, Torino, Italy | ATPG, BIST, Low-Power Testing, Fault Tolerant Design, Formal Verification | |
| Dr. Zoran Stamenkovic , IHP, Im Technologiepark 25 | Computer-Aided Design and Test of Integrated Circuits and Systems | |
| Dr. Bernd Steinbach , Professor and Head of Institute of Computer Science, Freiberg University of Mining and Technology | efficient solution of large Boolean problems, synthesis for testability, test pattern generation, verification, logic synthesis, analysis and optimization of digital components, test of software systems | |
| Ramesh Tekumalla , Sun Microsystems | Delay Fault testing, Embedded Core Testing, Sequential Logic Synthesis and optimization, CAD Algorithms, Fault Tolerance | |
| Nur A. Touba , Assistant Professor, University of Texas, Austin, TX | Design-for-Test, BIST, Core Testing, Reconfigurable Computing | |
| Enrico Tronci, Ph.D. , University of L'Aquila, Coppito 67100 L'Aquila, ITALY | Formal Methods, Model Checking, Embedded Systems, Discrete Event Systems | |
| Raymond Ubar, Ph.D , Technical University of Tallinn, Estonia | CAD, ATPG, DFT | |
| Shambhu Upadhyaya , SUNY at Buffalo | Random Testing, BIST, Memory Testing and Synthesis, Analog Systems Diagnosis | |
| Burnell G West , Engineering Advisor, Schlumberger ATE | Test System Architecture, Precision Timing, CAE, IC Development, ITC | |
| Chin-Long Wey , Professor of Electrical and Computer Engineering, Michigan State University | Test and fault diagnosis of analog/mixed-signal circuits. | |
| Mike W.T. WONG , Department of Electronic and Information Engineering, The Hong Kong Polytechnic University | Testing and fault diagnosis of analog and mixed-signal circuits, DFTs, fault tolerant design of digital systems | |
| Angus K. M. Wu , EDA Center, Department of Electronic Engineering, City University of Hong Kong | analog circuit test synthesis, low power vlsi, statistical power electronic design | |
| Cheng-Wen Wu , Dept. Electrical Engineering, National Tsing Hua University | Design and test of VLSI cores and systems | |
| Hans-Joachim Wunderlich , Computer Architecture, University of Stuttgart | BIST, test, fault-tolerance, SoC, online-test | |
| Teruhiko Yamada , Professor, Meiji University, Japan | Defect and Fault Model, Test & Diagnosis, DFT | |
| Dr Julian Yeandel , Senior IC Designer, Xemics SA | Integrated Circuit testing, fault location and fault tolerant design, low power digital Design. |